Commit 40fb1715 authored by Venki Pallipadi's avatar Venki Pallipadi Committed by Ingo Molnar
Browse files

x86: support always running TSC on Intel CPUs 



Impact: reward non-stop TSCs with good TSC-based clocksources, etc.

Add support for CPUID_0x80000007_Bit8 on Intel CPUs as well. This bit means
that the TSC is invariant with C/P/T states and always runs at constant
frequency.

With Intel CPUs, we have 3 classes
* CPUs where TSC runs at constant rate and does not stop n C-states
* CPUs where TSC runs at constant rate, but will stop in deep C-states
* CPUs where TSC rate will vary based on P/T-states and TSC will stop in deep
  C-states.

To cover these 3, one feature bit (CONSTANT_TSC) is not enough. So, add a
second bit (NONSTOP_TSC). CONSTANT_TSC indicates that the TSC runs at
constant frequency irrespective of P/T-states, and NONSTOP_TSC indicates
that TSC does not stop in deep C-states.

CPUID_0x8000000_Bit8 indicates both these feature bit can be set.
We still have CONSTANT_TSC _set_ and NONSTOP_TSC _not_set_ on some older Intel
CPUs, based on model checks. We can use TSC on such CPUs for time, as long as
those CPUs do not support/enter deep C-states.

Signed-off-by: default avatarVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 7e91a122

arch/x86/kernel/cpu/amd.c

+7 −2
Original line number Diff line number Diff line
@@ -283,9 +283,14 @@ static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 
{

	early_init_amd_mc(c);



	/* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */

	if (c->x86_power & (1<<8))

	/*

	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate

	 * with P/T states and does not stop in deep C-states

	 */

	if (c->x86_power & (1 << 8)) {

		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);

	}



#ifdef CONFIG_X86_64

	set_cpu_cap(c, X86_FEATURE_SYSCALL32);

arch/x86/kernel/cpu/intel.c

+10 −0
Original line number Diff line number Diff line
@@ -41,6 +41,16 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) 
	if (c->x86 == 15 && c->x86_cache_alignment == 64)

		c->x86_cache_alignment = 128;

#endif



	/*

	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate

	 * with P/T states and does not stop in deep C-states

	 */

	if (c->x86_power & (1 << 8)) {

		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);

		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);

	}



}



#ifdef CONFIG_X86_32

arch/x86/kernel/process.c

+1 −1
Original line number Diff line number Diff line
@@ -270,7 +270,7 @@ static void c1e_idle(void) 
		rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);

		if (lo & K8_INTP_C1E_ACTIVE_MASK) {

			c1e_detected = 1;

			if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))

			if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))

				mark_tsc_unstable("TSC halt in AMD C1E");

			printk(KERN_INFO "System has AMD C1E enabled\n");

			set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);

drivers/acpi/processor_idle.c

+3 −3
Original line number Diff line number Diff line
@@ -374,15 +374,15 @@ static int tsc_halts_in_c(int state) 
{

	switch (boot_cpu_data.x86_vendor) {

	case X86_VENDOR_AMD:

	case X86_VENDOR_INTEL:

		/*

		 * AMD Fam10h TSC will tick in all

		 * C/P/S0/S1 states when this bit is set.

		 */

		if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))

		if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC))

			return 0;



		/*FALL THROUGH*/

	case X86_VENDOR_INTEL:

		/* Several cases known where TSC halts in C2 too */

	default:

		return state > ACPI_STATE_C1;

	}

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