Commit 40f05e5b authored by Mark Starovoytov's avatar Mark Starovoytov Committed by David S. Miller
Browse files

net: atlantic: proper rss_ctrl1 (54c0) initialization 



This patch fixes an inconsistency between code and spec, which
was found while working on the QoS implementation.

When 8TCs are used, 2 is the maximum supported number of index bits.
In a 4TC mode, we do support 3, but we shouldn't really use the bytes,
which are intended for the 8TC mode.

Signed-off-by: default avatarMark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: default avatarIgor Russkikh <irusskikh@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2deac71a

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c

+14 −2
Original line number Diff line number Diff line
@@ -447,6 +447,19 @@ static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self) 
	return aq_hw_err_from_flags(self);

}



void hw_atl_b0_hw_init_rx_rss_ctrl1(struct aq_hw_s *self)

{

	struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;

	u32 rss_ctrl1 = HW_ATL_RSS_DISABLED;



	if (cfg->is_rss)

		rss_ctrl1 = (cfg->tc_mode == AQ_TC_MODE_8TCS) ?

			    HW_ATL_RSS_ENABLED_8TCS_2INDEX_BITS :

			    HW_ATL_RSS_ENABLED_4TCS_3INDEX_BITS;



	hw_atl_reg_rx_flr_rss_control1set(self, rss_ctrl1);

}



static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)

{

	struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
@@ -459,8 +472,7 @@ static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self) 
	hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);



	/* RSS Ring selection */

	hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?

					0xB3333333U : 0x00000000U);

	hw_atl_b0_hw_init_rx_rss_ctrl1(self);



	/* Multicast filters */

	for (i = HW_ATL_B0_MAC_MAX; i--;) {

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.h

+2 −0
Original line number Diff line number Diff line
@@ -58,6 +58,8 @@ int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self, 
int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self, struct aq_ring_s *ring);

int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self, struct aq_ring_s *ring);



void hw_atl_b0_hw_init_rx_rss_ctrl1(struct aq_hw_s *self);



int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr);



int hw_atl_b0_hw_start(struct aq_hw_s *self);

drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0_internal.h

+4 −0
Original line number Diff line number Diff line
@@ -151,6 +151,10 @@ 
#define HW_ATL_B0_MAX_RXD 8184U

#define HW_ATL_B0_MAX_TXD 8184U



#define HW_ATL_RSS_DISABLED 0x00000000U

#define HW_ATL_RSS_ENABLED_8TCS_2INDEX_BITS 0xA2222222U

#define HW_ATL_RSS_ENABLED_4TCS_3INDEX_BITS 0x80003333U



/* HW layer capabilities */



#endif /* HW_ATL_B0_INTERNAL_H */

drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2.c

+1 −3
Original line number Diff line number Diff line
@@ -475,9 +475,7 @@ static int hw_atl2_hw_init_rx_path(struct aq_hw_s *self) 
	hw_atl2_rpf_rss_hash_type_set(self, HW_ATL2_RPF_RSS_HASH_TYPE_ALL);



	/* RSS Ring selection */

	hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?

						HW_ATL_RSS_ENABLED_3INDEX_BITS :

						HW_ATL_RSS_DISABLED);

	hw_atl_b0_hw_init_rx_rss_ctrl1(self);



	/* Multicast filters */

	for (i = HW_ATL2_MAC_MAX; i--;) {

drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_internal.h

+0 −3
Original line number Diff line number Diff line
@@ -117,9 +117,6 @@ enum HW_ATL2_RPF_RSS_HASH_TYPE { 
					HW_ATL2_RPF_RSS_HASH_TYPE_IPV6_EX_UDP,

};



#define HW_ATL_RSS_DISABLED 0x00000000U

#define HW_ATL_RSS_ENABLED_3INDEX_BITS 0xB3333333U



#define HW_ATL_MCAST_FLT_ANY_TO_HOST 0x00010FFFU



struct hw_atl2_priv {

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