staging: tidspbridge: remove DBC_ASSERT macro (40e6336d) · Commits · 戴 / test

drivers/staging/tidspbridge/core/chnl_sm.c

+0 −12

Original line number	Diff line number	Diff line
		@@ -123,7 +123,6 @@ int bridge_chnl_add_io_req(struct chnl_object chnl_obj, void host_buf,
		CHNL_IS_OUTPUT(pchnl->chnl_mode))
		return -EPIPE;
		/* No other possible states left */
		DBC_ASSERT(0);
		}

		dev_obj = dev_get_first();
		@@ -190,7 +189,6 @@ func_cont:
		* Note: for dma chans dw_dsp_addr contains dsp address
		* of SM buffer.
		*/
		DBC_ASSERT(chnl_mgr_obj->word_size != 0);
		/* DSP address */
		chnl_packet_obj->dsp_tx_addr = dw_dsp_addr / chnl_mgr_obj->word_size;
		chnl_packet_obj->byte_size = byte_size;
		@@ -201,7 +199,6 @@ func_cont:
		CHNL_IOCSTATCOMPLETE);
		list_add_tail(&chnl_packet_obj->link, &pchnl->io_requests);
		pchnl->cio_reqs++;
		DBC_ASSERT(pchnl->cio_reqs <= pchnl->chnl_packets);
		/*
		* If end of stream, update the channel state to prevent
		* more IOR's.
		@@ -209,8 +206,6 @@ func_cont:
		if (is_eos)
		pchnl->state \|= CHNL_STATEEOS;

		/* Legacy DSM Processor-Copy */
		DBC_ASSERT(pchnl->chnl_type == CHNL_PCPY);
		/* Request IO from the DSP */
		io_request_chnl(chnl_mgr_obj->iomgr, pchnl,
		(CHNL_IS_INPUT(pchnl->chnl_mode) ? IO_INPUT :
		@@ -283,7 +278,6 @@ int bridge_chnl_cancel_io(struct chnl_object *chnl_obj)
		list_add_tail(&chirp->link, &pchnl->io_completions);
		pchnl->cio_cs++;
		pchnl->cio_reqs--;
		DBC_ASSERT(pchnl->cio_reqs >= 0);
		}

		spin_unlock_bh(&chnl_mgr_obj->chnl_mgr_lock);
		@@ -311,8 +305,6 @@ int bridge_chnl_close(struct chnl_object *chnl_obj)
		status = bridge_chnl_cancel_io(chnl_obj);
		if (status)
		return status;
		/* Assert I/O on this channel is now cancelled: Protects from io_dpc */
		DBC_ASSERT((pchnl->state & CHNL_STATECANCEL));
		/* Invalidate channel object: Protects from CHNL_GetIOCompletion() */
		/* Free the slot in the channel manager: */
		pchnl->chnl_mgr_obj->channels[pchnl->chnl_id] = NULL;
		@@ -367,7 +359,6 @@ int bridge_chnl_create(struct chnl_mgr **channel_mgr,
		* mgr_attrts->max_channels = CHNL_MAXCHANNELS =
		* DDMA_MAXDDMACHNLS = DDMA_MAXZCPYCHNLS.
		*/
		DBC_ASSERT(mgr_attrts->max_channels == CHNL_MAXCHANNELS);
		max_channels = CHNL_MAXCHANNELS + CHNL_MAXCHANNELS * CHNL_PCPY;
		/* Create array of channels */
		chnl_mgr_obj->channels = kzalloc(sizeof(struct chnl_object *)
		@@ -584,7 +575,6 @@ int bridge_chnl_get_ioc(struct chnl_object *chnl_obj, u32 timeout,
		omap_mbox_disable_irq(dev_ctxt->mbox, IRQ_RX);
		if (dequeue_ioc) {
		/* Dequeue IOC and set chan_ioc; */
		DBC_ASSERT(!list_empty(&pchnl->io_completions));
		chnl_packet_obj = list_first_entry(&pchnl->io_completions,
		struct chnl_irp, link);
		list_del(&chnl_packet_obj->link);
		@@ -748,7 +738,6 @@ int bridge_chnl_open(struct chnl_object **chnl,
		return status;
		}

		DBC_ASSERT(ch_id < chnl_mgr_obj->max_channels);

		/* Create channel object: */
		pchnl = kzalloc(sizeof(struct chnl_object), GFP_KERNEL);
		@@ -837,7 +826,6 @@ int bridge_chnl_register_notify(struct chnl_object *chnl_obj,
		{
		int status = 0;

		DBC_ASSERT(!(event_mask & ~(DSP_STREAMDONE \| DSP_STREAMIOCOMPLETION)));

		if (event_mask)
		status = ntfy_register(chnl_obj->ntfy_obj, hnotification,

drivers/staging/tidspbridge/core/io_sm.c

+0 −14

Original line number	Diff line number	Diff line
		@@ -973,29 +973,16 @@ void io_request_chnl(struct io_mgr io_manager, struct chnl_object pchnl,
		chnl_mgr_obj = io_manager->chnl_mgr;
		sm = io_manager->shared_mem;
		if (io_mode == IO_INPUT) {
		/*
		* Assertion fires if CHNL_AddIOReq() called on a stream
		* which was cancelled, or attached to a dead board.
		*/
		DBC_ASSERT((pchnl->state == CHNL_STATEREADY) \|\|
		(pchnl->state == CHNL_STATEEOS));
		/* Indicate to the DSP we have a buffer available for input */
		set_chnl_busy(sm, pchnl->chnl_id);
		*mbx_val = MBX_PCPY_CLASS;
		} else if (io_mode == IO_OUTPUT) {
		/*
		* This assertion fails if CHNL_AddIOReq() was called on a
		* stream which was cancelled, or attached to a dead board.
		*/
		DBC_ASSERT((pchnl->state & ~CHNL_STATEEOS) ==
		CHNL_STATEREADY);
		/*
		* Record the fact that we have a buffer available for
		* output.
		*/
		chnl_mgr_obj->output_mask \|= (1 << pchnl->chnl_id);
		} else {
		DBC_ASSERT(io_mode); /* Shouldn't get here. */
		}
		func_end:
		return;
		@@ -1087,7 +1074,6 @@ static void input_chnl(struct io_mgr pio_mgr, struct chnl_object pchnl,
		dw_arg = sm->arg;
		if (chnl_id >= CHNL_MAXCHANNELS) {
		/* Shouldn't be here: would indicate corrupted shm. */
		DBC_ASSERT(chnl_id);
		goto func_end;
		}
		pchnl = chnl_mgr_obj->channels[chnl_id];

drivers/staging/tidspbridge/core/tiomap3430.c

+0 −3

Original line number	Diff line number	Diff line
		@@ -396,16 +396,13 @@ static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
		(void)dev_get_symbol(dev_context->dev_obj, SHMBASENAME,
		&ul_shm_base_virt);
		ul_shm_base_virt *= DSPWORDSIZE;
		DBC_ASSERT(ul_shm_base_virt != 0);
		/* DSP Virtual address */
		ul_tlb_base_virt = dev_context->atlb_entry[0].dsp_va;
		DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);
		ul_shm_offset_virt =
		ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
		/* Kernel logical address */
		ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;

		DBC_ASSERT(ul_shm_base != 0);
		/* 2nd wd is used as sync field */
		dw_sync_addr = ul_shm_base + SHMSYNCOFFSET;
		/* Write a signature into the shm base + offset; this will

drivers/staging/tidspbridge/core/tiomap3430_pwr.c

+0 −1

Original line number	Diff line number	Diff line
		@@ -303,7 +303,6 @@ int dsp_peripheral_clk_ctrl(struct bridge_dev_context *dev_context,
		}
		/* TODO -- Assert may be a too hard restriction here.. May be we should
		* just return with failure when the CLK ID does not match */
		/* DBC_ASSERT(clk_id_index < MBX_PM_MAX_RESOURCES); */
		if (clk_id_index == MBX_PM_MAX_RESOURCES) {
		/* return with a more meaningfull error code */
		return -EPERM;

drivers/staging/tidspbridge/core/tiomap_io.c

+0 −15

Original line number	Diff line number	Diff line
		@@ -68,20 +68,17 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt,
		status = dev_get_symbol(dev_context->dev_obj,
		SHMBASENAME, &ul_shm_base_virt);
		}
		DBC_ASSERT(ul_shm_base_virt != 0);

		/* Check if it is a read of Trace section */
		if (!status && !ul_trace_sec_beg) {
		status = dev_get_symbol(dev_context->dev_obj,
		DSP_TRACESEC_BEG, &ul_trace_sec_beg);
		}
		DBC_ASSERT(ul_trace_sec_beg != 0);

		if (!status && !ul_trace_sec_end) {
		status = dev_get_symbol(dev_context->dev_obj,
		DSP_TRACESEC_END, &ul_trace_sec_end);
		}
		DBC_ASSERT(ul_trace_sec_end != 0);

		if (!status) {
		if ((dsp_addr <= ul_trace_sec_end) &&
		@@ -105,19 +102,16 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt,
		status = dev_get_symbol(dev_context->dev_obj,
		DYNEXTBASE, &ul_dyn_ext_base);
		}
		DBC_ASSERT(ul_dyn_ext_base != 0);

		if (!status) {
		status = dev_get_symbol(dev_context->dev_obj,
		EXTBASE, &ul_ext_base);
		}
		DBC_ASSERT(ul_ext_base != 0);

		if (!status) {
		status = dev_get_symbol(dev_context->dev_obj,
		EXTEND, &ul_ext_end);
		}
		DBC_ASSERT(ul_ext_end != 0);

		/* Trace buffer is right after the shm SEG0,
		* so set the base address to SHMBASE */
		@@ -126,8 +120,6 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt,
		ul_ext_end = ul_trace_sec_end;
		}

		DBC_ASSERT(ul_ext_end != 0);
		DBC_ASSERT(ul_ext_end > ul_ext_base);

		if (ul_ext_end < ul_ext_base)
		status = -EPERM;
		@@ -135,7 +127,6 @@ int read_ext_dsp_data(struct bridge_dev_context *dev_ctxt,
		if (!status) {
		ul_tlb_base_virt =
		dev_context->atlb_entry[0].dsp_va * DSPWORDSIZE;
		DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);
		dw_ext_prog_virt_mem =
		dev_context->atlb_entry[0].gpp_va;

		@@ -271,7 +262,6 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
		/* Get SHM_BEG EXT_BEG and EXT_END. */
		ret = dev_get_symbol(dev_context->dev_obj,
		SHMBASENAME, &ul_shm_base_virt);
		DBC_ASSERT(ul_shm_base_virt != 0);
		if (dynamic_load) {
		if (!ret) {
		if (symbols_reloaded)
		@@ -280,7 +270,6 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
		(dev_context->dev_obj, DYNEXTBASE,
		&ul_ext_base);
		}
		DBC_ASSERT(ul_ext_base != 0);
		if (!ret) {
		/* DR OMAPS00013235 : DLModules array may be
		* in EXTMEM. It is expected that DYNEXTMEM and
		@@ -299,7 +288,6 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
		dev_get_symbol
		(dev_context->dev_obj, EXTBASE,
		&ul_ext_base);
		DBC_ASSERT(ul_ext_base != 0);
		if (!ret)
		ret =
		dev_get_symbol
		@@ -312,15 +300,12 @@ int write_ext_dsp_data(struct bridge_dev_context *dev_context,
		if (trace_load)
		ul_ext_base = ul_shm_base_virt;

		DBC_ASSERT(ul_ext_end != 0);
		DBC_ASSERT(ul_ext_end > ul_ext_base);
		if (ul_ext_end < ul_ext_base)
		ret = -EPERM;

		if (!ret) {
		ul_tlb_base_virt =
		dev_context->atlb_entry[0].dsp_va * DSPWORDSIZE;
		DBC_ASSERT(ul_tlb_base_virt <= ul_shm_base_virt);

		if (symbols_reloaded) {
		ret = dev_get_symbol

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