Commit 40ddbf50 authored Aug 25, 2014 by Roger Quadros Committed by Tony Lindgren Aug 25, 2014

mtd: nand: omap: Fix 1-bit Hamming code scheme, omap_calculate_ecc()



commit 65b97cf6 introduced in v3.7 caused a regression
by using a reversed CS_MASK thus causing omap_calculate_ecc to
always fail. As the NAND base driver never checks for .calculate()'s
return value, the zeroed ECC values are used as is without showing
any error to the user. However, this won't work and the NAND device
won't be guarded by any error code.

Fix the issue by using the correct mask.

Code was tested on omap3beagle using the following procedure
- flash the primary bootloader (MLO) from the kernel to the first
NAND partition using nandwrite.
- boot the board from NAND. This utilizes OMAP ROM loader that
relies on 1-bit Hamming code ECC.

Fixes: 65b97cf6 (mtd: nand: omap2: handle nand on gpmc)

Cc: <stable@vger.kernel.org>	[3.7+]
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

parent d5c1eb17

drivers/mtd/nand/omap2.c

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -931,7 +931,7 @@ static int omap_calculate_ecc(struct mtd_info mtd, const u_char dat,
	u32 val;		u32 val;

	val = readl(info->reg.gpmc_ecc_config);		val = readl(info->reg.gpmc_ecc_config);
	if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)		if (((val >> ECC_CONFIG_CS_SHIFT) & CS_MASK) != info->gpmc_cs)
	return -EINVAL;		return -EINVAL;

	/* read ecc result */		/* read ecc result */

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