Commit 409a5f27 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'bcm_sf2-vlan' 



Florian Fainelli says:

====================
net: dsa: bcm_sf2: add VLAN support

This is long overdue, finally add support for VLANs in the Broadcom Starfigther
2 switch driver.

There are a few things that make us differ from e.g; mv88e6xxx.c:

- we keep a software cache of which VLANs are enabled and which are not to
  dramatically speed up the VLAN dump operation, we do not have any HW operation
  which would only return the list of valid VLAN entries, they would have to be
  all queried one by one, with 4K vlans, this takes a while

- the default behavior is equivalent to setting VLAN filtering to 1, still working
  on implementing a proper port_vlan_filtering callback, but I figured the most
  conservative behavior is probably okay anyway

- without enabling VLANs, the default behavior is to receive any 802.1q frames
  (per the DSA documentation), however, once we start enabling VLAN support, if
  an interface leaves the bridge, we still want it to receive all 802.1q frames
  so we utiliez the "Join all VLAN" feature of the switch to perform that
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents cf515802 9c57a771

drivers/net/dsa/bcm_sf2.c

+397 −127
Original line number Diff line number Diff line
@@ -461,19 +461,13 @@ static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port, 
	return 0;

}



/* Fast-ageing of ARL entries for a given port, equivalent to an ARL

 * flush for that port.

 */

static int bcm_sf2_sw_fast_age_port(struct dsa_switch  *ds, int port)

static int bcm_sf2_fast_age_op(struct bcm_sf2_priv *priv)

{

	struct bcm_sf2_priv *priv = ds_to_priv(ds);

	unsigned int timeout = 1000;

	u32 reg;



	core_writel(priv, port, CORE_FAST_AGE_PORT);



	reg = core_readl(priv, CORE_FAST_AGE_CTRL);

	reg |= EN_AGE_PORT | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE;

	reg |= EN_AGE_PORT | EN_AGE_VLAN | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE;

	core_writel(priv, reg, CORE_FAST_AGE_CTRL);



	do {
@@ -492,13 +486,98 @@ static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port) 
	return 0;

}



/* Fast-ageing of ARL entries for a given port, equivalent to an ARL

 * flush for that port.

 */

static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port)

{

	struct bcm_sf2_priv *priv = ds_to_priv(ds);



	core_writel(priv, port, CORE_FAST_AGE_PORT);



	return bcm_sf2_fast_age_op(priv);

}



static int bcm_sf2_sw_fast_age_vlan(struct bcm_sf2_priv *priv, u16 vid)

{

	core_writel(priv, vid, CORE_FAST_AGE_VID);



	return bcm_sf2_fast_age_op(priv);

}



static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv)

{

	unsigned int timeout = 10;

	u32 reg;



	do {

		reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL);

		if (!(reg & ARLA_VTBL_STDN))

			return 0;



		usleep_range(1000, 2000);

	} while (timeout--);



	return -ETIMEDOUT;

}



static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op)

{

	core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL);



	return bcm_sf2_vlan_op_wait(priv);

}



static void bcm_sf2_set_vlan_entry(struct bcm_sf2_priv *priv, u16 vid,

				   struct bcm_sf2_vlan *vlan)

{

	int ret;



	core_writel(priv, vid & VTBL_ADDR_INDEX_MASK, CORE_ARLA_VTBL_ADDR);

	core_writel(priv, vlan->untag << UNTAG_MAP_SHIFT | vlan->members,

		    CORE_ARLA_VTBL_ENTRY);



	ret = bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_WRITE);

	if (ret)

		pr_err("failed to write VLAN entry\n");

}



static int bcm_sf2_get_vlan_entry(struct bcm_sf2_priv *priv, u16 vid,

				  struct bcm_sf2_vlan *vlan)

{

	u32 entry;

	int ret;



	core_writel(priv, vid & VTBL_ADDR_INDEX_MASK, CORE_ARLA_VTBL_ADDR);



	ret = bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_READ);

	if (ret)

		return ret;



	entry = core_readl(priv, CORE_ARLA_VTBL_ENTRY);

	vlan->members = entry & FWD_MAP_MASK;

	vlan->untag = (entry >> UNTAG_MAP_SHIFT) & UNTAG_MAP_MASK;



	return 0;

}



static int bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,

			      struct net_device *bridge)

{

	struct bcm_sf2_priv *priv = ds_to_priv(ds);

	s8 cpu_port = ds->dst->cpu_port;

	unsigned int i;

	u32 reg, p_ctl;



	/* Make this port leave the all VLANs join since we will have proper

	 * VLAN entries from now on

	 */

	reg = core_readl(priv, CORE_JOIN_ALL_VLAN_EN);

	reg &= ~BIT(port);

	if ((reg & BIT(cpu_port)) == BIT(cpu_port))

		reg &= ~BIT(cpu_port);

	core_writel(priv, reg, CORE_JOIN_ALL_VLAN_EN);



	priv->port_sts[port].bridge_dev = bridge;

	p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
@@ -530,6 +609,7 @@ static void bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port) 
{

	struct bcm_sf2_priv *priv = ds_to_priv(ds);

	struct net_device *bridge = priv->port_sts[port].bridge_dev;

	s8 cpu_port = ds->dst->cpu_port;

	unsigned int i;

	u32 reg, p_ctl;
@@ -553,6 +633,13 @@ static void bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port) 
	core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));

	priv->port_sts[port].vlan_ctl_mask = p_ctl;

	priv->port_sts[port].bridge_dev = NULL;



	/* Make this port join all VLANs without VLAN entries */

	reg = core_readl(priv, CORE_JOIN_ALL_VLAN_EN);

	reg |= BIT(port);

	if (!(reg & BIT(cpu_port)))

		reg |= BIT(cpu_port);

	core_writel(priv, reg, CORE_JOIN_ALL_VLAN_EN);

}



static void bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
@@ -1059,125 +1146,6 @@ static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) 
		of_node_put(priv->master_mii_dn);

}



static int bcm_sf2_sw_setup(struct dsa_switch *ds)

{

	const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;

	struct bcm_sf2_priv *priv = ds_to_priv(ds);

	struct device_node *dn;

	void __iomem **base;

	unsigned int port;

	unsigned int i;

	u32 reg, rev;

	int ret;



	spin_lock_init(&priv->indir_lock);

	mutex_init(&priv->stats_mutex);



	/* All the interesting properties are at the parent device_node

	 * level

	 */

	dn = ds->cd->of_node->parent;

	bcm_sf2_identify_ports(priv, ds->cd->of_node);



	priv->irq0 = irq_of_parse_and_map(dn, 0);

	priv->irq1 = irq_of_parse_and_map(dn, 1);



	base = &priv->core;

	for (i = 0; i < BCM_SF2_REGS_NUM; i++) {

		*base = of_iomap(dn, i);

		if (*base == NULL) {

			pr_err("unable to find register: %s\n", reg_names[i]);

			ret = -ENOMEM;

			goto out_unmap;

		}

		base++;

	}



	ret = bcm_sf2_sw_rst(priv);

	if (ret) {

		pr_err("unable to software reset switch: %d\n", ret);

		goto out_unmap;

	}



	ret = bcm_sf2_mdio_register(ds);

	if (ret) {

		pr_err("failed to register MDIO bus\n");

		goto out_unmap;

	}



	/* Disable all interrupts and request them */

	bcm_sf2_intr_disable(priv);



	ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,

			  "switch_0", priv);

	if (ret < 0) {

		pr_err("failed to request switch_0 IRQ\n");

		goto out_unmap;

	}



	ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,

			  "switch_1", priv);

	if (ret < 0) {

		pr_err("failed to request switch_1 IRQ\n");

		goto out_free_irq0;

	}



	/* Reset the MIB counters */

	reg = core_readl(priv, CORE_GMNCFGCFG);

	reg |= RST_MIB_CNT;

	core_writel(priv, reg, CORE_GMNCFGCFG);

	reg &= ~RST_MIB_CNT;

	core_writel(priv, reg, CORE_GMNCFGCFG);



	/* Get the maximum number of ports for this switch */

	priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;

	if (priv->hw_params.num_ports > DSA_MAX_PORTS)

		priv->hw_params.num_ports = DSA_MAX_PORTS;



	/* Assume a single GPHY setup if we can't read that property */

	if (of_property_read_u32(dn, "brcm,num-gphy",

				 &priv->hw_params.num_gphy))

		priv->hw_params.num_gphy = 1;



	/* Enable all valid ports and disable those unused */

	for (port = 0; port < priv->hw_params.num_ports; port++) {

		/* IMP port receives special treatment */

		if ((1 << port) & ds->enabled_port_mask)

			bcm_sf2_port_setup(ds, port, NULL);

		else if (dsa_is_cpu_port(ds, port))

			bcm_sf2_imp_setup(ds, port);

		else

			bcm_sf2_port_disable(ds, port, NULL);

	}



	rev = reg_readl(priv, REG_SWITCH_REVISION);

	priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &

					SWITCH_TOP_REV_MASK;

	priv->hw_params.core_rev = (rev & SF2_REV_MASK);



	rev = reg_readl(priv, REG_PHY_REVISION);

	priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;



	pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",

		priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,

		priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,

		priv->core, priv->irq0, priv->irq1);



	return 0;



out_free_irq0:

	free_irq(priv->irq0, priv);

out_unmap:

	base = &priv->core;

	for (i = 0; i < BCM_SF2_REGS_NUM; i++) {

		if (*base)

			iounmap(*base);

		base++;

	}

	bcm_sf2_mdio_unregister(priv);

	return ret;

}



static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)

{

	return 0;
@@ -1425,6 +1393,303 @@ static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, 
	return p->ethtool_ops->set_wol(p, wol);

}



static void bcm_sf2_enable_vlan(struct bcm_sf2_priv *priv, bool enable)

{

	u32 mgmt, vc0, vc1, vc4, vc5;



	mgmt = core_readl(priv, CORE_SWMODE);

	vc0 = core_readl(priv, CORE_VLAN_CTRL0);

	vc1 = core_readl(priv, CORE_VLAN_CTRL1);

	vc4 = core_readl(priv, CORE_VLAN_CTRL4);

	vc5 = core_readl(priv, CORE_VLAN_CTRL5);



	mgmt &= ~SW_FWDG_MODE;



	if (enable) {

		vc0 |= VLAN_EN | VLAN_LEARN_MODE_IVL;

		vc1 |= EN_RSV_MCAST_UNTAG | EN_RSV_MCAST_FWDMAP;

		vc4 &= ~(INGR_VID_CHK_MASK << INGR_VID_CHK_SHIFT);

		vc4 |= INGR_VID_CHK_DROP;

		vc5 |= DROP_VTABLE_MISS | EN_VID_FFF_FWD;

	} else {

		vc0 &= ~(VLAN_EN | VLAN_LEARN_MODE_IVL);

		vc1 &= ~(EN_RSV_MCAST_UNTAG | EN_RSV_MCAST_FWDMAP);

		vc4 &= ~(INGR_VID_CHK_MASK << INGR_VID_CHK_SHIFT);

		vc5 &= ~(DROP_VTABLE_MISS | EN_VID_FFF_FWD);

		vc4 |= INGR_VID_CHK_VID_VIOL_IMP;

	}



	core_writel(priv, vc0, CORE_VLAN_CTRL0);

	core_writel(priv, vc1, CORE_VLAN_CTRL1);

	core_writel(priv, 0, CORE_VLAN_CTRL3);

	core_writel(priv, vc4, CORE_VLAN_CTRL4);

	core_writel(priv, vc5, CORE_VLAN_CTRL5);

	core_writel(priv, mgmt, CORE_SWMODE);

}



static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds)

{

	struct bcm_sf2_priv *priv = ds_to_priv(ds);

	unsigned int port;



	/* Clear all VLANs */

	bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR);



	for (port = 0; port < priv->hw_params.num_ports; port++) {

		if (!((1 << port) & ds->enabled_port_mask))

			continue;



		core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port));

	}

}



static int bcm_sf2_sw_vlan_filtering(struct dsa_switch *ds, int port,

				     bool vlan_filtering)

{

	return 0;

}



static int bcm_sf2_sw_vlan_prepare(struct dsa_switch *ds, int port,

				   const struct switchdev_obj_port_vlan *vlan,

				   struct switchdev_trans *trans)

{

	struct bcm_sf2_priv *priv = ds_to_priv(ds);



	bcm_sf2_enable_vlan(priv, true);



	return 0;

}



static void bcm_sf2_sw_vlan_add(struct dsa_switch *ds, int port,

				const struct switchdev_obj_port_vlan *vlan,

				struct switchdev_trans *trans)

{

	struct bcm_sf2_priv *priv = ds_to_priv(ds);

	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;

	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;

	s8 cpu_port = ds->dst->cpu_port;

	struct bcm_sf2_vlan *vl;

	u16 vid;



	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {

		vl = &priv->vlans[vid];



		bcm_sf2_get_vlan_entry(priv, vid, vl);



		vl->members |= BIT(port) | BIT(cpu_port);

		if (untagged)

			vl->untag |= BIT(port) | BIT(cpu_port);

		else

			vl->untag &= ~(BIT(port) | BIT(cpu_port));



		bcm_sf2_set_vlan_entry(priv, vid, vl);

		bcm_sf2_sw_fast_age_vlan(priv, vid);

	}



	if (pvid) {

		core_writel(priv, vlan->vid_end, CORE_DEFAULT_1Q_TAG_P(port));

		core_writel(priv, vlan->vid_end,

			    CORE_DEFAULT_1Q_TAG_P(cpu_port));

		bcm_sf2_sw_fast_age_vlan(priv, vid);

	}

}



static int bcm_sf2_sw_vlan_del(struct dsa_switch *ds, int port,

			       const struct switchdev_obj_port_vlan *vlan)

{

	struct bcm_sf2_priv *priv = ds_to_priv(ds);

	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;

	s8 cpu_port = ds->dst->cpu_port;

	struct bcm_sf2_vlan *vl;

	u16 vid, pvid;

	int ret;



	pvid = core_readl(priv, CORE_DEFAULT_1Q_TAG_P(port));



	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {

		vl = &priv->vlans[vid];



		ret = bcm_sf2_get_vlan_entry(priv, vid, vl);

		if (ret)

			return ret;



		vl->members &= ~BIT(port);

		if ((vl->members & BIT(cpu_port)) == BIT(cpu_port))

			vl->members = 0;

		if (pvid == vid)

			pvid = 0;

		if (untagged) {

			vl->untag &= ~BIT(port);

			if ((vl->untag & BIT(port)) == BIT(cpu_port))

				vl->untag = 0;

		}



		bcm_sf2_set_vlan_entry(priv, vid, vl);

		bcm_sf2_sw_fast_age_vlan(priv, vid);

	}



	core_writel(priv, pvid, CORE_DEFAULT_1Q_TAG_P(port));

	core_writel(priv, pvid, CORE_DEFAULT_1Q_TAG_P(cpu_port));

	bcm_sf2_sw_fast_age_vlan(priv, vid);



	return 0;

}



static int bcm_sf2_sw_vlan_dump(struct dsa_switch *ds, int port,

				struct switchdev_obj_port_vlan *vlan,

				int (*cb)(struct switchdev_obj *obj))

{

	struct bcm_sf2_priv *priv = ds_to_priv(ds);

	struct bcm_sf2_port_status *p = &priv->port_sts[port];

	struct bcm_sf2_vlan *vl;

	u16 vid, pvid;

	int err = 0;



	pvid = core_readl(priv, CORE_DEFAULT_1Q_TAG_P(port));



	for (vid = 0; vid < VLAN_N_VID; vid++) {

		vl = &priv->vlans[vid];



		if (!(vl->members & BIT(port)))

			continue;



		vlan->vid_begin = vlan->vid_end = vid;

		vlan->flags = 0;



		if (vl->untag & BIT(port))

			vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;

		if (p->pvid == vid)

			vlan->flags |= BRIDGE_VLAN_INFO_PVID;



		err = cb(&vlan->obj);

		if (err)

			break;

	}



	return err;

}



static int bcm_sf2_sw_setup(struct dsa_switch *ds)

{

	const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;

	struct bcm_sf2_priv *priv = ds_to_priv(ds);

	struct device_node *dn;

	void __iomem **base;

	unsigned int port;

	unsigned int i;

	u32 reg, rev;

	int ret;



	spin_lock_init(&priv->indir_lock);

	mutex_init(&priv->stats_mutex);



	/* All the interesting properties are at the parent device_node

	 * level

	 */

	dn = ds->cd->of_node->parent;

	bcm_sf2_identify_ports(priv, ds->cd->of_node);



	priv->irq0 = irq_of_parse_and_map(dn, 0);

	priv->irq1 = irq_of_parse_and_map(dn, 1);



	base = &priv->core;

	for (i = 0; i < BCM_SF2_REGS_NUM; i++) {

		*base = of_iomap(dn, i);

		if (*base == NULL) {

			pr_err("unable to find register: %s\n", reg_names[i]);

			ret = -ENOMEM;

			goto out_unmap;

		}

		base++;

	}



	ret = bcm_sf2_sw_rst(priv);

	if (ret) {

		pr_err("unable to software reset switch: %d\n", ret);

		goto out_unmap;

	}



	ret = bcm_sf2_mdio_register(ds);

	if (ret) {

		pr_err("failed to register MDIO bus\n");

		goto out_unmap;

	}



	/* Disable all interrupts and request them */

	bcm_sf2_intr_disable(priv);



	ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,

			  "switch_0", priv);

	if (ret < 0) {

		pr_err("failed to request switch_0 IRQ\n");

		goto out_unmap;

	}



	ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,

			  "switch_1", priv);

	if (ret < 0) {

		pr_err("failed to request switch_1 IRQ\n");

		goto out_free_irq0;

	}



	/* Reset the MIB counters */

	reg = core_readl(priv, CORE_GMNCFGCFG);

	reg |= RST_MIB_CNT;

	core_writel(priv, reg, CORE_GMNCFGCFG);

	reg &= ~RST_MIB_CNT;

	core_writel(priv, reg, CORE_GMNCFGCFG);



	/* Get the maximum number of ports for this switch */

	priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;

	if (priv->hw_params.num_ports > DSA_MAX_PORTS)

		priv->hw_params.num_ports = DSA_MAX_PORTS;



	/* Assume a single GPHY setup if we can't read that property */

	if (of_property_read_u32(dn, "brcm,num-gphy",

				 &priv->hw_params.num_gphy))

		priv->hw_params.num_gphy = 1;



	/* Enable all valid ports and disable those unused */

	for (port = 0; port < priv->hw_params.num_ports; port++) {

		/* IMP port receives special treatment */

		if ((1 << port) & ds->enabled_port_mask)

			bcm_sf2_port_setup(ds, port, NULL);

		else if (dsa_is_cpu_port(ds, port))

			bcm_sf2_imp_setup(ds, port);

		else

			bcm_sf2_port_disable(ds, port, NULL);

	}



	bcm_sf2_sw_configure_vlan(ds);



	rev = reg_readl(priv, REG_SWITCH_REVISION);

	priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &

					SWITCH_TOP_REV_MASK;

	priv->hw_params.core_rev = (rev & SF2_REV_MASK);



	rev = reg_readl(priv, REG_PHY_REVISION);

	priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;



	pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",

		priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,

		priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,

		priv->core, priv->irq0, priv->irq1);



	return 0;



out_free_irq0:

	free_irq(priv->irq0, priv);

out_unmap:

	base = &priv->core;

	for (i = 0; i < BCM_SF2_REGS_NUM; i++) {

		if (*base)

			iounmap(*base);

		base++;

	}

	bcm_sf2_mdio_unregister(priv);

	return ret;

}



static struct dsa_switch_driver bcm_sf2_switch_driver = {

	.tag_protocol		= DSA_TAG_PROTO_BRCM,

	.probe			= bcm_sf2_sw_drv_probe,
@@ -1451,6 +1716,11 @@ static struct dsa_switch_driver bcm_sf2_switch_driver = { 
	.port_fdb_add		= bcm_sf2_sw_fdb_add,

	.port_fdb_del		= bcm_sf2_sw_fdb_del,

	.port_fdb_dump		= bcm_sf2_sw_fdb_dump,

	.port_vlan_filtering	= bcm_sf2_sw_vlan_filtering,

	.port_vlan_prepare	= bcm_sf2_sw_vlan_prepare,

	.port_vlan_add		= bcm_sf2_sw_vlan_add,

	.port_vlan_del		= bcm_sf2_sw_vlan_del,

	.port_vlan_dump		= bcm_sf2_sw_vlan_dump,

};



static int __init bcm_sf2_init(void)

drivers/net/dsa/bcm_sf2.h

+10 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 
#include <linux/ethtool.h>

#include <linux/types.h>

#include <linux/bitops.h>

#include <linux/if_vlan.h>



#include <net/dsa.h>
@@ -50,6 +51,7 @@ struct bcm_sf2_port_status { 
	struct ethtool_eee eee;



	u32 vlan_ctl_mask;

	u16 pvid;



	struct net_device *bridge_dev;

};
@@ -63,6 +65,11 @@ struct bcm_sf2_arl_entry { 
	u8 is_static:1;

};



struct bcm_sf2_vlan {

	u16 members;

	u16 untag;

};



static inline void bcm_sf2_mac_from_u64(u64 src, u8 *dst)

{

	unsigned int i;
@@ -148,6 +155,9 @@ struct bcm_sf2_priv { 
	struct device_node		*master_mii_dn;

	struct mii_bus			*slave_mii_bus;

	struct mii_bus			*master_mii_bus;



	/* Cache of programmed VLANs */

	struct bcm_sf2_vlan		vlans[VLAN_N_VID];

};



struct bcm_sf2_hw_stats {

drivers/net/dsa/bcm_sf2_regs.h

+70 −0
Original line number Diff line number Diff line
@@ -274,6 +274,23 @@ 
#define CORE_ARLA_SRCH_RSLT_MACVID(x)	(CORE_ARLA_SRCH_RSLT_0_MACVID + ((x) * 0x40))

#define CORE_ARLA_SRCH_RSLT(x)		(CORE_ARLA_SRCH_RSLT_0 + ((x) * 0x40))



#define CORE_ARLA_VTBL_RWCTRL		0x1600

#define  ARLA_VTBL_CMD_WRITE		0

#define  ARLA_VTBL_CMD_READ		1

#define  ARLA_VTBL_CMD_CLEAR		2

#define  ARLA_VTBL_STDN			(1 << 7)



#define CORE_ARLA_VTBL_ADDR		0x1604

#define  VTBL_ADDR_INDEX_MASK		0xfff



#define CORE_ARLA_VTBL_ENTRY		0x160c

#define  FWD_MAP_MASK			0x1ff

#define  UNTAG_MAP_MASK			0x1ff

#define  UNTAG_MAP_SHIFT		9

#define  MSTP_INDEX_MASK		0x7

#define  MSTP_INDEX_SHIFT		18

#define  FWD_MODE			(1 << 21)



#define CORE_MEM_PSM_VDD_CTRL		0x2380

#define  P_TXQ_PSM_VDD_SHIFT		2

#define  P_TXQ_PSM_VDD_MASK		0x3
@@ -287,6 +304,59 @@ 
#define CORE_PORT_VLAN_CTL_PORT(x)	(0xc400 + ((x) * 0x8))

#define  PORT_VLAN_CTRL_MASK		0x1ff



#define CORE_VLAN_CTRL0			0xd000

#define  CHANGE_1P_VID_INNER		(1 << 0)

#define  CHANGE_1P_VID_OUTER		(1 << 1)

#define  CHANGE_1Q_VID			(1 << 3)

#define  VLAN_LEARN_MODE_SVL		(0 << 5)

#define  VLAN_LEARN_MODE_IVL		(3 << 5)

#define  VLAN_EN			(1 << 7)



#define CORE_VLAN_CTRL1			0xd004

#define  EN_RSV_MCAST_FWDMAP		(1 << 2)

#define  EN_RSV_MCAST_UNTAG		(1 << 3)

#define  EN_IPMC_BYPASS_FWDMAP		(1 << 5)

#define  EN_IPMC_BYPASS_UNTAG		(1 << 6)



#define CORE_VLAN_CTRL2			0xd008

#define  EN_MIIM_BYPASS_V_FWDMAP	(1 << 2)

#define  EN_GMRP_GVRP_V_FWDMAP		(1 << 5)

#define  EN_GMRP_GVRP_UNTAG_MAP		(1 << 6)



#define CORE_VLAN_CTRL3			0xd00c

#define  EN_DROP_NON1Q_MASK		0x1ff



#define CORE_VLAN_CTRL4			0xd014

#define  RESV_MCAST_FLOOD		(1 << 1)

#define  EN_DOUBLE_TAG_MASK		0x3

#define  EN_DOUBLE_TAG_SHIFT		2

#define  EN_MGE_REV_GMRP		(1 << 4)

#define  EN_MGE_REV_GVRP		(1 << 5)

#define  INGR_VID_CHK_SHIFT		6

#define  INGR_VID_CHK_MASK		0x3

#define  INGR_VID_CHK_FWD		(0 << INGR_VID_CHK_SHIFT)

#define  INGR_VID_CHK_DROP		(1 << INGR_VID_CHK_SHIFT)

#define  INGR_VID_CHK_NO_CHK		(2 << INGR_VID_CHK_SHIFT)

#define  INGR_VID_CHK_VID_VIOL_IMP	(3 << INGR_VID_CHK_SHIFT)



#define CORE_VLAN_CTRL5			0xd018

#define  EN_CPU_RX_BYP_INNER_CRCCHCK	(1 << 0)

#define  EN_VID_FFF_FWD			(1 << 2)

#define  DROP_VTABLE_MISS		(1 << 3)

#define  EGRESS_DIR_FRM_BYP_TRUNK_EN	(1 << 4)

#define  PRESV_NON1Q			(1 << 6)



#define CORE_VLAN_CTRL6			0xd01c

#define  STRICT_SFD_DETECT		(1 << 0)

#define  DIS_ARL_BUST_LMIT		(1 << 4)



#define CORE_DEFAULT_1Q_TAG_P(x)	(0xd040 + ((x) * 8))

#define  CFI_SHIFT			12

#define  PRI_SHIFT			13

#define  PRI_MASK			0x7



#define CORE_JOIN_ALL_VLAN_EN		0xd140



#define CORE_EEE_EN_CTRL		0x24800

#define CORE_EEE_LPI_INDICATE		0x24810

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