Commit 40978ac6 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/nbio6.1: add hw bug workaround for vega10/12 



Configure PCIE_CI_CNTL to work around a hw bug that affects
some multi-GPU compute workloads.

Acked-by: default avatarFeifei Xu <Feifei.Xu@amd.com>
Reviewed-by: default avatarHarish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c2c2ce1e

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

+7 −0
Original line number Diff line number Diff line
@@ -32,6 +32,7 @@ 
#define smnCPM_CONTROL                                                                                  0x11180460

#define smnPCIE_CNTL2                                                                                   0x11180070

#define smnPCIE_CONFIG_CNTL                                                                             0x11180044

#define smnPCIE_CI_CNTL                                                                                 0x11180080



static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)

{
@@ -270,6 +271,12 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev) 


	if (def != data)

		WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);



	def = data = RREG32_PCIE(smnPCIE_CI_CNTL);

	data = REG_SET_FIELD(data, PCIE_CI_CNTL, CI_SLV_ORDERING_DIS, 1);



	if (def != data)

		WREG32_PCIE(smnPCIE_CI_CNTL, data);

}



const struct amdgpu_nbio_funcs nbio_v6_1_funcs = {

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