Merge tag 'irqchip-5.5' of...

- interrupts: specifies the interrupt line(s) in the interrupt-parent controller

  node; valid values depend on the type of parent interrupt controller

Optional properties:

- brcm,irq-can-wake: If present, this means the L1 controller can be used as a

  wakeup source for system suspend/resume.

Optional properties:

- brcm,int-fwd-mask: if present, a bit mask to indicate which interrupts

  have already been configured by the firmware and should be left unmanaged.

  This should have one 32-bit word per status/set/clear/mask group.

If multiple reg ranges and interrupt-parent entries are present on an SMP

system, the driver will allow IRQ SMP affinity to be set up through the

/proc/irq/ interface.  In the simplest possible configuration, only one

* Freescale Layerscape external IRQs

Some Layerscape SOCs (LS1021A, LS1043A, LS1046A) support inverting

the polarity of certain external interrupt lines.

The device node must be a child of the node representing the

Supplemental Configuration Unit (SCFG).

Required properties:

- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq".

- #interrupt-cells: Must be 2. The first element is the index of the

  external interrupt line. The second element is the trigger type.

- #address-cells: Must be 0.

- interrupt-controller: Identifies the node as an interrupt controller

- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in

  the SCFG.

- interrupt-map: Specifies the mapping from external interrupts to GIC

  interrupts.

- interrupt-map-mask: Must be <0xffffffff 0>.

Example:

	scfg: scfg@1570000 {

		compatible = "fsl,ls1021a-scfg", "syscon";

		reg = <0x0 0x1570000 0x0 0x10000>;

		big-endian;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges = <0x0 0x0 0x1570000 0x10000>;

		extirq: interrupt-controller@1ac {

			compatible = "fsl,ls1021a-extirq";

			#interrupt-cells = <2>;

			#address-cells = <0>;

			interrupt-controller;

			reg = <0x1ac 4>;

			interrupt-map =

				<0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,

				<1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,

				<2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,

				<3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,

				<4 0 &gic GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,

				<5 0 &gic GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-map-mask = <0xffffffff 0x0>;

		};

	};

	interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,

			      <&extirq 1 IRQ_TYPE_LEVEL_LOW>;

			sensitivity = <7>;

		};

	};

3) Interrupt wakeup parent

--------------------------

Some interrupt controllers in a SoC, are always powered on and have a select

interrupts routed to them, so that they can wakeup the SoC from suspend. These

interrupt controllers do not fall into the category of a parent interrupt

controller and can be specified by the "wakeup-parent" property and contain a

single phandle referring to the wakeup capable interrupt controller.

   Example:

	wakeup-parent = <&pdc_intc>;

- compatible:

	Usage: required

	Value type: <string>

	Definition: Should contain "qcom,<soc>-pdc"

	Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"

		    - "qcom,sc7180-pdc": For SC7180

		    - "qcom,sdm845-pdc": For SDM845

- reg:

 * GITS_VPENDBASER - the Valid bit must be cleared before changing

 * anything else.

 */

static inline void gits_write_vpendbaser(u64 val, void * __iomem addr)

static inline void gits_write_vpendbaser(u64 val, void __iomem *addr)

{

	u32 tmp;