Commit 40713189 authored by Thara Gopinath's avatar Thara Gopinath Committed by Kevin Hilman
Browse files

OMAP3: PM: Set/clear T2 bit for Smartreflex on TWL 



Voltage control on TWL can be done using VMODE/I2C1/I2C_SR.
Since almost all platforms use I2C_SR on omap3, omap3_twl_init by
default expects that OMAP's I2C_SR is plugged in to TWL's I2C
and calls omap3_twl_set_sr_bit. On platforms where I2C_SR is not connected,
the board files are expected to call omap3_twl_set_sr_bit(false) to
ensure that I2C_SR path is not set for voltage control and prevent
the default behavior of omap3_twl_init.

Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Signed-off-by: default avatarThara Gopinath <thara@ti.com>
Signed-off-by: default avatarShweta Gulati <shweta.gulati@ti.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: default avatarKevin Hilman <khilman@ti.com>
parent 8c5ca4d2

arch/arm/mach-omap2/omap_twl.c

+60 −0
Original line number Diff line number Diff line
@@ -59,8 +59,15 @@ 


static bool is_offset_valid;

static u8 smps_offset;

/*

 * Flag to ensure Smartreflex bit in TWL

 * being cleared in board file is not overwritten.

 */

static bool __initdata twl_sr_enable_autoinit;



#define TWL4030_DCDC_GLOBAL_CFG        0x06

#define REG_SMPS_OFFSET         0xE0

#define SMARTREFLEX_ENABLE     BIT(3)



static unsigned long twl4030_vsel_to_uv(const u8 vsel)

{
@@ -269,6 +276,18 @@ int __init omap3_twl_init(void) 
		omap3_core_volt_info.vp_vddmax = OMAP3630_VP2_VLIMITTO_VDDMAX;

	}



	/*

	 * The smartreflex bit on twl4030 specifies if the setting of voltage

	 * is done over the I2C_SR path. Since this setting is independent of

	 * the actual usage of smartreflex AVS module, we enable TWL SR bit

	 * by default irrespective of whether smartreflex AVS module is enabled

	 * on the OMAP side or not. This is because without this bit enabled,

	 * the voltage scaling through vp forceupdate/bypass mechanism of

	 * voltage scaling will not function on TWL over I2C_SR.

	 */

	if (!twl_sr_enable_autoinit)

		omap3_twl_set_sr_bit(true);



	voltdm = omap_voltage_domain_lookup("mpu");

	omap_voltage_register_pmic(voltdm, &omap3_mpu_volt_info);
@@ -277,3 +296,44 @@ int __init omap3_twl_init(void) 


	return 0;

}



/**

 * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL

 * @enable: enable SR mode in twl or not

 *

 * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure

 * voltage scaling through OMAP SR works. Else, the smartreflex bit

 * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but

 * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct

 * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,

 * in those scenarios this bit is to be cleared (enable = false).

 *

 * Returns 0 on sucess, error is returned if I2C read/write fails.

 */

int __init omap3_twl_set_sr_bit(bool enable)

{

	u8 temp;

	int ret;

	if (twl_sr_enable_autoinit)

		pr_warning("%s: unexpected multiple calls\n", __func__);



	ret = twl_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &temp,

					TWL4030_DCDC_GLOBAL_CFG);

	if (ret)

		goto err;



	if (enable)

		temp |= SMARTREFLEX_ENABLE;

	else

		temp &= ~SMARTREFLEX_ENABLE;



	ret = twl_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, temp,

				TWL4030_DCDC_GLOBAL_CFG);

	if (!ret) {

		twl_sr_enable_autoinit = true;

		return 0;

	}

err:

	pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);

	return ret;

}

arch/arm/mach-omap2/pm.h

+1 −0
Original line number Diff line number Diff line
@@ -127,6 +127,7 @@ static inline void omap_enable_smartreflex_on_init(void) {} 
#ifdef CONFIG_TWL4030_CORE

extern int omap3_twl_init(void);

extern int omap4_twl_init(void);

extern int omap3_twl_set_sr_bit(bool enable);

#else

static inline int omap3_twl_init(void)

{

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