Commit 4035e812 authored by Vladimir Oltean's avatar Vladimir Oltean Committed by David S. Miller
Browse files

net: phy: mscc: rename enum rgmii_rx_clock_delay to rgmii_clock_delay 



There is nothing RX-specific about these clock skew values. So remove
"RX" from the name in preparation for the next patch where TX delays are
also going to be configured.

Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 69ccaf25

drivers/net/phy/mscc/mscc.h

+9 −9
Original line number Diff line number Diff line
@@ -12,15 +12,15 @@ 
#include "mscc_macsec.h"

#endif



enum rgmii_rx_clock_delay {

	RGMII_RX_CLK_DELAY_0_2_NS = 0,

	RGMII_RX_CLK_DELAY_0_8_NS = 1,

	RGMII_RX_CLK_DELAY_1_1_NS = 2,

	RGMII_RX_CLK_DELAY_1_7_NS = 3,

	RGMII_RX_CLK_DELAY_2_0_NS = 4,

	RGMII_RX_CLK_DELAY_2_3_NS = 5,

	RGMII_RX_CLK_DELAY_2_6_NS = 6,

	RGMII_RX_CLK_DELAY_3_4_NS = 7

enum rgmii_clock_delay {

	RGMII_CLK_DELAY_0_2_NS = 0,

	RGMII_CLK_DELAY_0_8_NS = 1,

	RGMII_CLK_DELAY_1_1_NS = 2,

	RGMII_CLK_DELAY_1_7_NS = 3,

	RGMII_CLK_DELAY_2_0_NS = 4,

	RGMII_CLK_DELAY_2_3_NS = 5,

	RGMII_CLK_DELAY_2_6_NS = 6,

	RGMII_CLK_DELAY_3_4_NS = 7

};



/* Microsemi VSC85xx PHY registers */

drivers/net/phy/mscc/mscc_main.c

+1 −1
Original line number Diff line number Diff line
@@ -525,7 +525,7 @@ static int vsc85xx_default_config(struct phy_device *phydev) 
	phydev->mdix_ctrl = ETH_TP_MDI_AUTO;

	mutex_lock(&phydev->lock);



	reg_val = RGMII_RX_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;

	reg_val = RGMII_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS;



	rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2,

			      MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK,

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