Commit 402b0042 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v4.18-tag1' of... 

Merge tag 'clk-renesas-for-v4.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull renesas clk driver updates from Geert Uytterhoeven:

  - Add support for the MSIOF module clocks on R-Car M3-N
  - Add support for the new RZ/G1C and R-Car E3 SoCs

* tag 'clk-renesas-for-v4.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Add support for R-Car E3
  clk: renesas: Add r8a77990 CPG Core Clock Definitions
  clk: renesas: rcar-gen2: Centralize quirks handling
  clk: renesas: r8a77980: Correct parent clock of PCIEC0
  clk: renesas: r8a7794: Fix LB clock divider
  clk: renesas: r8a7792: Fix LB clock divider
  clk: renesas: r8a7791/r8a7793: Fix LB clock divider
  clk: renesas: r8a7745: Fix LB clock divider
  clk: renesas: r8a7743: Fix LB clock divider
  clk: renesas: cpg-mssr: Add r8a77470 support
  clk: renesas: Add r8a77470 CPG Core Clock Definitions
  clk: renesas: r8a77965: Add MSIOF controller clocks
parents 60cc43fc 3570a2af

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt

+7 −3
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ Required Properties: 
  - compatible: Must be one of:

      - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)

      - "renesas,r8a7745-cpg-mssr" for the r8a7745 SoC (RZ/G1E)

      - "renesas,r8a77470-cpg-mssr" for the r8a77470 SoC (RZ/G1C)

      - "renesas,r8a7790-cpg-mssr" for the r8a7790 SoC (R-Car H2)

      - "renesas,r8a7791-cpg-mssr" for the r8a7791 SoC (R-Car M2-W)

      - "renesas,r8a7792-cpg-mssr" for the r8a7792 SoC (R-Car V2H)
@@ -25,6 +26,7 @@ Required Properties: 
      - "renesas,r8a77965-cpg-mssr" for the r8a77965 SoC (R-Car M3-N)

      - "renesas,r8a77970-cpg-mssr" for the r8a77970 SoC (R-Car V3M)

      - "renesas,r8a77980-cpg-mssr" for the r8a77980 SoC (R-Car V3H)

      - "renesas,r8a77990-cpg-mssr" for the r8a77990 SoC (R-Car E3)

      - "renesas,r8a77995-cpg-mssr" for the r8a77995 SoC (R-Car D3)



  - reg: Base address and length of the memory resource used by the CPG/MSSR
@@ -33,10 +35,12 @@ Required Properties: 
  - clocks: References to external parent clocks, one entry for each entry in

    clock-names

  - clock-names: List of external parent clock names. Valid names are:

      - "extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7792, r8a7793, r8a7794,

		 r8a7795, r8a7796, r8a77965, r8a77970, r8a77980, r8a77995)

      - "extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7792,

		 r8a7793, r8a7794, r8a7795, r8a7796, r8a77965, r8a77970,

		 r8a77980, r8a77990, r8a77995)

      - "extalr" (r8a7795, r8a7796, r8a77965, r8a77970, r8a77980)

      - "usb_extal" (r8a7743, r8a7745, r8a7790, r8a7791, r8a7793, r8a7794)

      - "usb_extal" (r8a7743, r8a7745, r8a77470, r8a7790, r8a7791, r8a7793,

		     r8a7794)



  - #clock-cells: Must be 2

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

drivers/clk/renesas/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ config CLK_RENESAS 
	select CLK_R8A7740 if ARCH_R8A7740

	select CLK_R8A7743 if ARCH_R8A7743

	select CLK_R8A7745 if ARCH_R8A7745

	select CLK_R8A77470 if ARCH_R8A77470

	select CLK_R8A7778 if ARCH_R8A7778

	select CLK_R8A7779 if ARCH_R8A7779

	select CLK_R8A7790 if ARCH_R8A7790
@@ -18,6 +19,7 @@ config CLK_RENESAS 
	select CLK_R8A77965 if ARCH_R8A77965

	select CLK_R8A77970 if ARCH_R8A77970

	select CLK_R8A77980 if ARCH_R8A77980

	select CLK_R8A77990 if ARCH_R8A77990

	select CLK_R8A77995 if ARCH_R8A77995

	select CLK_SH73A0 if ARCH_SH73A0
@@ -60,6 +62,10 @@ config CLK_R8A7745 
	bool "RZ/G1E clock support" if COMPILE_TEST

	select CLK_RCAR_GEN2_CPG



config CLK_R8A77470

	bool "RZ/G1C clock support" if COMPILE_TEST

	select CLK_RCAR_GEN2_CPG



config CLK_R8A7778

	bool "R-Car M1A clock support" if COMPILE_TEST

	select CLK_RENESAS_CPG_MSTP
@@ -111,6 +117,10 @@ config CLK_R8A77980 
	bool "R-Car V3H clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG



config CLK_R8A77990

	bool "R-Car E3 clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG



config CLK_R8A77995

	bool "R-Car D3 clock support" if COMPILE_TEST

	select CLK_RCAR_GEN3_CPG

drivers/clk/renesas/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ obj-$(CONFIG_CLK_R8A73A4) += clk-r8a73a4.o 
obj-$(CONFIG_CLK_R8A7740)		+= clk-r8a7740.o

obj-$(CONFIG_CLK_R8A7743)		+= r8a7743-cpg-mssr.o

obj-$(CONFIG_CLK_R8A7745)		+= r8a7745-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77470)		+= r8a77470-cpg-mssr.o

obj-$(CONFIG_CLK_R8A7778)		+= clk-r8a7778.o

obj-$(CONFIG_CLK_R8A7779)		+= clk-r8a7779.o

obj-$(CONFIG_CLK_R8A7790)		+= r8a7790-cpg-mssr.o
@@ -17,6 +18,7 @@ obj-$(CONFIG_CLK_R8A7796) += r8a7796-cpg-mssr.o 
obj-$(CONFIG_CLK_R8A77965)		+= r8a77965-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77970)		+= r8a77970-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77980)		+= r8a77980-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77990)		+= r8a77990-cpg-mssr.o

obj-$(CONFIG_CLK_R8A77995)		+= r8a77995-cpg-mssr.o

obj-$(CONFIG_CLK_SH73A0)		+= clk-sh73a0.o

drivers/clk/renesas/r8a7743-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -52,7 +52,6 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = { 


	/* Core Clock Outputs */

	DEF_BASE("z",    R8A7743_CLK_Z,    CLK_TYPE_GEN2_Z,	CLK_PLL0),

	DEF_BASE("lb",   R8A7743_CLK_LB,   CLK_TYPE_GEN2_LB,	CLK_PLL1),

	DEF_BASE("sdh",  R8A7743_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),

	DEF_BASE("sd0",  R8A7743_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),

	DEF_BASE("qspi", R8A7743_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7743_core_clks[] __initconst = { 
	DEF_FIXED("zs",    R8A7743_CLK_ZS,	CLK_PLL1,	    6, 1),

	DEF_FIXED("hp",    R8A7743_CLK_HP,	CLK_PLL1,	   12, 1),

	DEF_FIXED("b",     R8A7743_CLK_B,	CLK_PLL1,	   12, 1),

	DEF_FIXED("lb",    R8A7743_CLK_LB,	CLK_PLL1,	   24, 1),

	DEF_FIXED("p",     R8A7743_CLK_P,	CLK_PLL1,	   24, 1),

	DEF_FIXED("cl",    R8A7743_CLK_CL,	CLK_PLL1,	   48, 1),

	DEF_FIXED("m2",    R8A7743_CLK_M2,	CLK_PLL1,	    8, 1),

drivers/clk/renesas/r8a7745-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,6 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = { 
	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2, CLK_PLL1, 2, 1),



	/* Core Clock Outputs */

	DEF_BASE("lb",   R8A7745_CLK_LB,   CLK_TYPE_GEN2_LB,	CLK_PLL1),

	DEF_BASE("sdh",  R8A7745_CLK_SDH,  CLK_TYPE_GEN2_SDH,	CLK_PLL1),

	DEF_BASE("sd0",  R8A7745_CLK_SD0,  CLK_TYPE_GEN2_SD0,	CLK_PLL1),

	DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI,	CLK_PLL1_DIV2),
@@ -63,6 +62,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = { 
	DEF_FIXED("zs",    R8A7745_CLK_ZS,	CLK_PLL1,	    6, 1),

	DEF_FIXED("hp",    R8A7745_CLK_HP,	CLK_PLL1,	   12, 1),

	DEF_FIXED("b",     R8A7745_CLK_B,	CLK_PLL1,	   12, 1),

	DEF_FIXED("lb",    R8A7745_CLK_LB,	CLK_PLL1,	   24, 1),

	DEF_FIXED("p",     R8A7745_CLK_P,	CLK_PLL1,	   24, 1),

	DEF_FIXED("cl",    R8A7745_CLK_CL,	CLK_PLL1,	   48, 1),

	DEF_FIXED("cp",    R8A7745_CLK_CP,	CLK_PLL1,	   48, 1),

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