Commit 4018fba4 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by Simon Horman
Browse files

ARM: dts: blanche: initial device tree 



Add the initial device  tree for the R8A7792 SoC based Blanche board.
The board has 2 debug serial ports: SCIF0 and SCIF3; include support for
them,  so that  the serial console  can  work.

Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 6bc734c6

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -638,6 +638,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ 
	r8a7790-lager.dtb \

	r8a7791-koelsch.dtb \

	r8a7791-porter.dtb \

	r8a7792-blanche.dtb \

	r8a7793-gose.dtb \

	r8a7794-alt.dtb \

	r8a7794-silk.dtb \

arch/arm/boot/dts/r8a7792-blanche.dts

0 → 100644
+45 −0
Original line number Diff line number Diff line 
/*

 * Device Tree Source for the Blanche board

 *

 * Copyright (C) 2014 Renesas Electronics Corporation

 * Copyright (C) 2016 Cogent  Embedded, Inc.

 *

 * This file is licensed under the terms of the GNU General Public License

 * version 2.  This program is licensed "as is" without any warranty of any

 * kind, whether express or implied.

 */



/dts-v1/;

#include "r8a7792.dtsi"



/ {

	model = "Blanche";

	compatible = "renesas,blanche", "renesas,r8a7792";



	aliases {

		serial0 = &scif0;

		serial1 = &scif3;

	};



	chosen {

		bootargs = "ignore_loglevel";

		stdout-path = "serial0:115200n8";

	};



	memory@40000000 {

		device_type = "memory";

		reg = <0 0x40000000 0 0x40000000>;

	};

};



&extal_clk {

	clock-frequency = <20000000>;

};



&scif0 {

	status = "okay";

};



&scif3 {

	status = "okay";

};

CRA Git | Maintained and supported by SUSTech CRA and CCSE