Commit 40118824 authored by Gregory CLEMENT's avatar Gregory CLEMENT
Browse files

ARM64: dts: marvell: add NAND support on the CP110 



The NAND controller used in A7K/A8K is present on the CP110. It is
compatible with the pxa-nand driver.

However, due to the limiation of the pins available this controller is
only usable on the CPM for A7K and on the CPS for A8K.

Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 9be778f6

arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -249,6 +249,21 @@ 
				status = "disabled";

			};



			cpm_nand: nand@720000 {

				/*

				 * Due to the limiation of the pin available

				 * this controller is only usable on the CPM

				 * for A7K and on the CPS for A8K.

				 */

				compatible = "marvell,armada370-nand";

				reg = <0x720000 0x54>;

				#address-cells = <1>;

				#size-cells = <1>;

				interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&cpm_clk 1 2>;

				status = "disabled";

			};



			cpm_trng: trng@760000 {

				compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";

				reg = <0x760000 0x7d>;

arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -250,6 +250,21 @@ 
				status = "disabled";

			};



			cps_nand: nand@720000 {

				/*

				 * Due to the limiation of the pin available

				 * this controller is only usable on the CPM

				 * for A7K and on the CPS for A8K.

				 */

				compatible = "marvell,armada370-nand";

				reg = <0x720000 0x54>;

				#address-cells = <1>;

				#size-cells = <1>;

				interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&cps_clk 1 2>;

				status = "disabled";

			};



			cps_trng: trng@760000 {

				compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";

				reg = <0x760000 0x7d>;

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