Merge branch 'hwmon-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging (4005af65) · Commits · 戴 / test

Documentation/hwmon/coretemp

+21 −1

Original line number	Diff line number	Diff line
		@@ -6,7 +6,9 @@ Supported chips:
		Prefix: 'coretemp'
		CPUID: family 0x6, models 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
		0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
		0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield)
		0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
		0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
		0x36 (Cedar Trail Atom)
		Datasheet: Intel 64 and IA-32 Architectures Software Developer's Manual
		Volume 3A: System Programming Guide
		http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
		@@ -52,6 +54,17 @@ Some information comes from ark.intel.com

		Process Processor TjMax(C)

		22nm Core i5/i7 Processors
		i7 3920XM, 3820QM, 3720QM, 3667U, 3520M 105
		i5 3427U, 3360M/3320M 105
		i7 3770/3770K 105
		i5 3570/3570K, 3550, 3470/3450 105
		i7 3770S 103
		i5 3570S/3550S, 3475S/3470S/3450S 103
		i7 3770T 94
		i5 3570T 94
		i5 3470T 91

		32nm Core i3/i5/i7 Processors
		i7 660UM/640/620, 640LM/620, 620M, 610E 105
		i5 540UM/520/430, 540M/520/450/430 105
		@@ -65,6 +78,11 @@ Process Processor TjMax(C)
		U3400 105
		P4505/P4500 90

		32nm Atom Processors
		Z2460 90
		D2700/2550/2500 100
		N2850/2800/2650/2600 100

		45nm Xeon Processors 5400 Quad-Core
		X5492, X5482, X5472, X5470, X5460, X5450 85
		E5472, E5462, E5450/40/30/20/10/05 85
		@@ -85,6 +103,8 @@ Process Processor TjMax(C)
		N475/470/455/450 100
		N280/270 90
		330/230 125
		E680/660/640/620 90
		E680T/660T/640T/620T 110

		45nm Core2 Processors
		Solo ULV SU3500/3300 100

drivers/hwmon/coretemp.c

+31 −2

Original line number	Diff line number	Diff line
		@@ -191,6 +191,24 @@ static ssize_t show_temp(struct device *dev,
		return tdata->valid ? sprintf(buf, "%d\n", tdata->temp) : -EAGAIN;
		}

		struct tjmax {
		char const *id;
		int tjmax;
		};

		static struct tjmax __cpuinitconst tjmax_table[] = {
		{ "CPU D410", 100000 },
		{ "CPU D425", 100000 },
		{ "CPU D510", 100000 },
		{ "CPU D525", 100000 },
		{ "CPU N450", 100000 },
		{ "CPU N455", 100000 },
		{ "CPU N470", 100000 },
		{ "CPU N475", 100000 },
		{ "CPU 230", 100000 },
		{ "CPU 330", 125000 },
		};

		static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,
		struct device *dev)
		{
		@@ -202,6 +220,13 @@ static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,
		int err;
		u32 eax, edx;
		struct pci_dev *host_bridge;
		int i;

		/* explicit tjmax table entries override heuristics */
		for (i = 0; i < ARRAY_SIZE(tjmax_table); i++) {
		if (strstr(c->x86_model_id, tjmax_table[i].id))
		return tjmax_table[i].tjmax;
		}

		/* Early chips have no MSR for TjMax */

		@@ -210,7 +235,8 @@ static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,

		/* Atom CPUs */

		if (c->x86_model == 0x1c) {
		if (c->x86_model == 0x1c \|\| c->x86_model == 0x26
		\|\| c->x86_model == 0x27) {
		usemsr_ee = 0;

		host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
		@@ -223,6 +249,9 @@ static int __cpuinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id,
		tjmax = 90000;

		pci_dev_put(host_bridge);
		} else if (c->x86_model == 0x36) {
		usemsr_ee = 0;
		tjmax = 100000;
		}

		if (c->x86_model > 0xe && usemsr_ee) {
		@@ -772,7 +801,7 @@ MODULE_DEVICE_TABLE(x86cpu, coretemp_ids);

		static int __init coretemp_init(void)
		{
		int i, err = -ENODEV;
		int i, err;

		/*
		* CPUID.06H.EAX[0] indicates whether the CPU has thermal

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