Commit 3ff98548 authored by Oak Zeng's avatar Oak Zeng Committed by Alex Deucher
Browse files

drm/amdgpu: Export function to flush TLB of specific vm hub 



This is for kfd to reuse amdgpu TLB invalidation function.
On gfx10, kfd only needs to flush TLB on gfx hub but not
on mm hub. So export a function for KFD flush TLB only on
specific hub.

Signed-off-by: default avatarOak Zeng <Oak.Zeng@amd.com>
Reviewed-by: default avatarChristian Konig <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 675a9e38

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c

+8 −4
Original line number Diff line number Diff line
@@ -670,7 +670,7 @@ static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid, 
int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid)

{

	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;

	int vmid;

	int vmid, i;

	struct amdgpu_ring *ring = &adev->gfx.kiq.ring;

	uint32_t flush_type = 0;
@@ -689,8 +689,9 @@ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 
		if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid(kgd, vmid)) {

			if (kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid(kgd, vmid)

				== pasid) {

				for (i = 0; i < adev->num_vmhubs; i++)

					amdgpu_gmc_flush_gpu_tlb(adev, vmid,

							 flush_type);

								i, flush_type);

				break;

			}

		}
@@ -702,6 +703,7 @@ int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 
int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid)

{

	struct amdgpu_device *adev = (struct amdgpu_device *) kgd;

	int i;



	if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) {

		pr_err("non kfd vmid %d\n", vmid);
@@ -723,7 +725,9 @@ int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 
	 * TODO 2: support range-based invalidation, requires kfg2kgd

	 * interface change

	 */

	amdgpu_gmc_flush_gpu_tlb(adev, vmid, 0);

	for (i = 0; i < adev->num_vmhubs; i++)

		amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c

+6 −3
Original line number Diff line number Diff line
@@ -251,7 +251,9 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 
	}

	mb();

	amdgpu_asic_flush_hdp(adev, NULL);

	amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);

	for (i = 0; i < adev->num_vmhubs; i++)

		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);



	return 0;

}
@@ -312,7 +314,7 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS

	unsigned i,t,p;

#endif

	int r;

	int r, i;



	if (!adev->gart.ready) {

		WARN(1, "trying to bind memory to uninitialized GART !\n");
@@ -336,7 +338,8 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 


	mb();

	amdgpu_asic_flush_hdp(adev, NULL);

	amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);

	for (i = 0; i < adev->num_vmhubs; i++)

		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);

	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h

+3 −3
Original line number Diff line number Diff line
@@ -89,8 +89,8 @@ struct amdgpu_vmhub { 
 */

struct amdgpu_gmc_funcs {

	/* flush the vm tlb via mmio */

	void (*flush_gpu_tlb)(struct amdgpu_device *adev,

			      uint32_t vmid, uint32_t flush_type);

	void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid,

				uint32_t vmhub, uint32_t flush_type);

	/* flush the vm tlb via ring */

	uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,

				       uint64_t pd_addr);
@@ -181,7 +181,7 @@ struct amdgpu_gmc { 
	struct ras_common_if    *mmhub_ras_if;

};



#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, type) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (type))

#define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))

#define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))

#define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))

#define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags))

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+4 −1
Original line number Diff line number Diff line
@@ -1748,9 +1748,12 @@ static void gfx_v10_0_init_csb(struct amdgpu_device *adev) 


static void gfx_v10_0_init_pg(struct amdgpu_device *adev)

{

	int i;



	gfx_v10_0_init_csb(adev);



	amdgpu_gmc_flush_gpu_tlb(adev, 0, 0);

	for (i = 0; i < adev->num_vmhubs; i++)

		amdgpu_gmc_flush_gpu_tlb(adev, 0, i, 0);



	/* TODO: init power gating */

	return;

drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

+12 −4
Original line number Diff line number Diff line
@@ -230,8 +230,8 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid, 
 *

 * Flush the TLB for the requested page table.

 */

static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev,

				    uint32_t vmid, uint32_t flush_type)

static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,

					uint32_t vmhub, uint32_t flush_type)

{

	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;

	struct dma_fence *fence;
@@ -244,7 +244,14 @@ static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, 


	mutex_lock(&adev->mman.gtt_window_lock);



	if (vmhub == AMDGPU_MMHUB_0) {

		gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);

		mutex_unlock(&adev->mman.gtt_window_lock);

		return;

	}



	BUG_ON(vmhub != AMDGPU_GFXHUB_0);



	if (!adev->mman.buffer_funcs_enabled ||

	    !adev->ib_pool_ready ||

	    adev->in_gpu_reset) {
@@ -756,7 +763,8 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) 


	gfxhub_v2_0_set_fault_enable_default(adev, value);

	mmhub_v2_0_set_fault_enable_default(adev, value);

	gmc_v10_0_flush_gpu_tlb(adev, 0, 0);

	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);

	gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);



	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",

		 (unsigned)(adev->gmc.gart_size >> 20),

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