Commit 3fb725c4 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:
 "Another set of five fixes.  The most interesting one is a fix for race
  condition in the local_irq_disable() implementation used by .S code
  for pre-MIPS R2 processors only.  It leaves a race that's hard but not
  impossible to hit; the others fairly obvious"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: Make local_irq_disable macro safe for non-Mipsr2
  MIPS: Octeon: Fix warning in of_device_alloc on cn3xxx
  MIPS: ftrace: Tweak safe_load()/safe_store() macros
  MIPS: BCM47XX: Check all (32) GPIOs when looking for a pin
  MIPS: Fix possible build error with transparent hugepages enabled
parents 92f99731 71ca7588

arch/mips/Kconfig

+6 −6
Original line number Diff line number Diff line
@@ -1776,12 +1776,12 @@ endchoice 


config FORCE_MAX_ZONEORDER

	int "Maximum zone order"

	range 14 64 if HUGETLB_PAGE && PAGE_SIZE_64KB

	default "14" if HUGETLB_PAGE && PAGE_SIZE_64KB

	range 13 64 if HUGETLB_PAGE && PAGE_SIZE_32KB

	default "13" if HUGETLB_PAGE && PAGE_SIZE_32KB

	range 12 64 if HUGETLB_PAGE && PAGE_SIZE_16KB

	default "12" if HUGETLB_PAGE && PAGE_SIZE_16KB

	range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB

	default "14" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB

	range 13 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB

	default "13" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_32KB

	range 12 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB

	default "12" if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_16KB

	range 11 64

	default "11"

	help

arch/mips/bcm47xx/nvram.c

+1 −1
Original line number Diff line number Diff line
@@ -196,7 +196,7 @@ int bcm47xx_nvram_gpio_pin(const char *name) 
	char nvram_var[10];

	char buf[30];



	for (i = 0; i < 16; i++) {

	for (i = 0; i < 32; i++) {

		err = snprintf(nvram_var, sizeof(nvram_var), "gpio%i", i);

		if (err <= 0)

			continue;

arch/mips/cavium-octeon/octeon-irq.c

+12 −10
Original line number Diff line number Diff line
@@ -975,10 +975,6 @@ static int octeon_irq_ciu_xlat(struct irq_domain *d, 
	if (ciu > 1 || bit > 63)

		return -EINVAL;



	/* These are the GPIO lines */

	if (ciu == 0 && bit >= 16 && bit < 32)

		return -EINVAL;



	*out_hwirq = (ciu << 6) | bit;

	*out_type = 0;
@@ -1007,6 +1003,10 @@ static int octeon_irq_ciu_map(struct irq_domain *d, 
	if (!octeon_irq_virq_in_range(virq))

		return -EINVAL;



	/* Don't map irq if it is reserved for GPIO. */

	if (line == 0 && bit >= 16 && bit <32)

		return 0;



	if (line > 1 || octeon_irq_ciu_to_irq[line][bit] != 0)

		return -EINVAL;
@@ -1525,10 +1525,6 @@ static int octeon_irq_ciu2_xlat(struct irq_domain *d, 
	ciu = intspec[0];

	bit = intspec[1];



	/* Line 7  are the GPIO lines */

	if (ciu > 6 || bit > 63)

		return -EINVAL;



	*out_hwirq = (ciu << 6) | bit;

	*out_type = 0;
@@ -1570,8 +1566,14 @@ static int octeon_irq_ciu2_map(struct irq_domain *d, 
	if (!octeon_irq_virq_in_range(virq))

		return -EINVAL;



	/* Line 7  are the GPIO lines */

	if (line > 6 || octeon_irq_ciu_to_irq[line][bit] != 0)

	/*

	 * Don't map irq if it is reserved for GPIO.

	 * (Line 7 are the GPIO lines.)

	 */

	if (line == 7)

		return 0;



	if (line > 7 || octeon_irq_ciu_to_irq[line][bit] != 0)

		return -EINVAL;



	if (octeon_irq_ciu2_is_edge(line, bit))

arch/mips/include/asm/asmmacro.h

+11 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#define _ASM_ASMMACRO_H



#include <asm/hazards.h>

#include <asm/asm-offsets.h>



#ifdef CONFIG_32BIT

#include <asm/asmmacro-32.h>
@@ -54,11 +55,21 @@ 
	.endm



	.macro	local_irq_disable reg=t0

#ifdef CONFIG_PREEMPT

	lw      \reg, TI_PRE_COUNT($28)

	addi    \reg, \reg, 1

	sw      \reg, TI_PRE_COUNT($28)

#endif

	mfc0	\reg, CP0_STATUS

	ori	\reg, \reg, 1

	xori	\reg, \reg, 1

	mtc0	\reg, CP0_STATUS

	irq_disable_hazard

#ifdef CONFIG_PREEMPT

	lw      \reg, TI_PRE_COUNT($28)

	addi    \reg, \reg, -1

	sw      \reg, TI_PRE_COUNT($28)

#endif

	.endm

#endif /* CONFIG_MIPS_MT_SMTC */

arch/mips/include/asm/ftrace.h

+10 −10
Original line number Diff line number Diff line
@@ -22,12 +22,12 @@ extern void _mcount(void); 
#define safe_load(load, src, dst, error)		\

do {							\

	asm volatile (					\

		"1: " load " %[" STR(dst) "], 0(%[" STR(src) "])\n"\

		"   li %[" STR(error) "], 0\n"		\

		"1: " load " %[tmp_dst], 0(%[tmp_src])\n"	\

		"   li %[tmp_err], 0\n"			\

		"2:\n"					\

							\

		".section .fixup, \"ax\"\n"		\

		"3: li %[" STR(error) "], 1\n"		\

		"3: li %[tmp_err], 1\n"			\

		"   j 2b\n"				\

		".previous\n"				\

							\
@@ -35,8 +35,8 @@ do { \ 
		STR(PTR) "\t1b, 3b\n\t"			\

		".previous\n"				\

							\

		: [dst] "=&r" (dst), [error] "=r" (error)\

		: [src] "r" (src)			\

		: [tmp_dst] "=&r" (dst), [tmp_err] "=r" (error)\

		: [tmp_src] "r" (src)			\

		: "memory"				\

	);						\

} while (0)
@@ -44,12 +44,12 @@ do { \ 
#define safe_store(store, src, dst, error)	\

do {						\

	asm volatile (				\

		"1: " store " %[" STR(src) "], 0(%[" STR(dst) "])\n"\

		"   li %[" STR(error) "], 0\n"	\

		"1: " store " %[tmp_src], 0(%[tmp_dst])\n"\

		"   li %[tmp_err], 0\n"		\

		"2:\n"				\

						\

		".section .fixup, \"ax\"\n"	\

		"3: li %[" STR(error) "], 1\n"	\

		"3: li %[tmp_err], 1\n"		\

		"   j 2b\n"			\

		".previous\n"			\

						\
@@ -57,8 +57,8 @@ do { \ 
		STR(PTR) "\t1b, 3b\n\t"		\

		".previous\n"			\

						\

		: [error] "=r" (error)		\

		: [dst] "r" (dst), [src] "r" (src)\

		: [tmp_err] "=r" (error)	\

		: [tmp_dst] "r" (dst), [tmp_src] "r" (src)\

		: "memory"			\

	);					\

} while (0)

CRA Git | Maintained and supported by SUSTech CRA and CCSE