Commit 3fb22b05 authored by Florian Fainelli's avatar Florian Fainelli Committed by David S. Miller
Browse files

net: dsa: b53: Implement software reset for 58xx devices 



Implement the correct software reset sequence for 58xx devices by
setting all 3 reset bits and polling for the SW_RST bit to clear itself
without a given timeout. We cannot use is58xx() here because that would
also include the 7445/7278 Starfighter 2 which have their own driver
doing the reset earlier on due to the HW specific integration.

Fixes: 991a36bb ("net: dsa: b53: Add support for BCM585xx/586xx/88312 integrated switch")
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent a424f0de

drivers/net/dsa/b53/b53_common.c

+24 −1
Original line number Diff line number Diff line
@@ -608,7 +608,8 @@ static void b53_switch_reset_gpio(struct b53_device *dev) 


static int b53_switch_reset(struct b53_device *dev)

{

	u8 mgmt;

	unsigned int timeout = 1000;

	u8 mgmt, reg;



	b53_switch_reset_gpio(dev);
@@ -617,6 +618,28 @@ static int b53_switch_reset(struct b53_device *dev) 
		b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);

	}



	/* This is specific to 58xx devices here, do not use is58xx() which

	 * covers the larger Starfigther 2 family, including 7445/7278 which

	 * still use this driver as a library and need to perform the reset

	 * earlier.

	 */

	if (dev->chip_id == BCM58XX_DEVICE_ID) {

		b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);

		reg |= SW_RST | EN_SW_RST | EN_CH_RST;

		b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);



		do {

			b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);

			if (!(reg & SW_RST))

				break;



			usleep_range(1000, 2000);

		} while (timeout-- > 0);



		if (timeout == 0)

			return -ETIMEDOUT;

	}



	b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);



	if (!(mgmt & SM_SW_FWD_EN)) {

drivers/net/dsa/b53/b53_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -143,6 +143,7 @@ 
/* Software reset register (8 bit) */

#define B53_SOFTRESET			0x79

#define   SW_RST			BIT(7)

#define   EN_CH_RST			BIT(6)

#define   EN_SW_RST			BIT(4)



/* Fast Aging Control register (8 bit) */

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