Commit 3faae981 authored Mar 02, 2020 by Tina Zhang Committed by Zhenyu Wang Mar 17, 2020

drm/i915/gvt: Add some regs to force-to-nonpriv whitelist



Those regs are added in order to slove the following complains:

 [70811.201818] gvt: vgpu(1) Invalid FORCE_NONPRIV write 2341 at offset 24d8
 [70811.201825] gvt: vgpu(1) Invalid FORCE_NONPRIV write 2351 at offset 24dc
 [70811.201831] gvt: vgpu(1) Invalid FORCE_NONPRIV write 10000d82 at offset 24e0
 [70811.201837] gvt: vgpu(1) Invalid FORCE_NONPRIV write 10064844 at offset 24e4

So solve them by adding the required regs to the whitelist.

Signed-off-by: Tina Zhang <tina.zhang@intel.com>
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20200302083130.17831-1-tina.zhang@intel.com

parent a61ac1e7

drivers/gpu/drm/i915/gvt/handlers.c

+6 −2

Original line number	Diff line number	Diff line
		@@ -462,11 +462,14 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
		return 0;
		}

		/* ascendingly sorted */
		/* sorted in ascending order */
		static i915_reg_t force_nonpriv_white_list[] = {
		_MMIO(0xd80),
		GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
		GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
		CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
		PS_INVOCATION_COUNT, //_MMIO(0x2348)
		PS_DEPTH_COUNT, //_MMIO(0x2350)
		GEN8_CS_CHICKEN1,//_MMIO(0x2580)
		_MMIO(0x2690),
		_MMIO(0x2694),
		@@ -491,6 +494,7 @@ static i915_reg_t force_nonpriv_white_list[] = {
		_MMIO(0xe18c),
		_MMIO(0xe48c),
		_MMIO(0xe5f4),
		_MMIO(0x64844),
		};

		/* a simple bsearch */

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