Commit 3fa2252b authored by Stephen Boyd's avatar Stephen Boyd Committed by Mike Turquette
Browse files

clk: Add set_rate_and_parent() op 



Some of Qualcomm's clocks can change their parent and rate at the
same time with a single register write. Add support for this
hardware to the common clock framework by adding a new
set_rate_and_parent() op. When the clock framework determines
that both the parent and the rate are going to change during
clk_set_rate() it will call the .set_rate_and_parent() op if
available and fall back to calling .set_parent() followed by
.set_rate() otherwise.

Reviewed-by: default avatarJames Hogan <james.hogan@imgtec.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent d0d44dd4

Documentation/clk.txt

+3 −0
Original line number Diff line number Diff line
@@ -77,6 +77,9 @@ the operations defined in clk.h: 
		int		(*set_parent)(struct clk_hw *hw, u8 index);

		u8		(*get_parent)(struct clk_hw *hw);

		int		(*set_rate)(struct clk_hw *hw, unsigned long);

		int		(*set_rate_and_parent)(struct clk_hw *hw,

					    unsigned long rate,

					    unsigned long parent_rate, u8 index);

		unsigned long	(*recalc_accuracy)(struct clk_hw *hw,

						   unsigned long parent_accuracy);

		void		(*init)(struct clk_hw *hw);

drivers/clk/clk.c

+59 −19
Original line number Diff line number Diff line
@@ -1218,10 +1218,9 @@ static void clk_reparent(struct clk *clk, struct clk *new_parent) 
	clk->parent = new_parent;

}



static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)

static struct clk *__clk_set_parent_before(struct clk *clk, struct clk *parent)

{

	unsigned long flags;

	int ret = 0;

	struct clk *old_parent = clk->parent;



	/*
@@ -1252,6 +1251,34 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index) 
	clk_reparent(clk, parent);

	clk_enable_unlock(flags);



	return old_parent;

}



static void __clk_set_parent_after(struct clk *clk, struct clk *parent,

		struct clk *old_parent)

{

	/*

	 * Finish the migration of prepare state and undo the changes done

	 * for preventing a race with clk_enable().

	 */

	if (clk->prepare_count) {

		clk_disable(clk);

		clk_disable(old_parent);

		__clk_unprepare(old_parent);

	}



	/* update debugfs with new clk tree topology */

	clk_debug_reparent(clk, parent);

}



static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index)

{

	unsigned long flags;

	int ret = 0;

	struct clk *old_parent;



	old_parent = __clk_set_parent_before(clk, parent);



	/* change clock input source */

	if (parent && clk->ops->set_parent)

		ret = clk->ops->set_parent(clk->hw, p_index);
@@ -1269,18 +1296,8 @@ static int __clk_set_parent(struct clk *clk, struct clk *parent, u8 p_index) 
		return ret;

	}



	/*

	 * Finish the migration of prepare state and undo the changes done

	 * for preventing a race with clk_enable().

	 */

	if (clk->prepare_count) {

		clk_disable(clk);

		clk_disable(old_parent);

		__clk_unprepare(old_parent);

	}

	__clk_set_parent_after(clk, parent, old_parent);



	/* update debugfs with new clk tree topology */

	clk_debug_reparent(clk, parent);

	return 0;

}
@@ -1465,17 +1482,32 @@ static void clk_change_rate(struct clk *clk) 
	struct clk *child;

	unsigned long old_rate;

	unsigned long best_parent_rate = 0;

	bool skip_set_rate = false;

	struct clk *old_parent;



	old_rate = clk->rate;



	/* set parent */

	if (clk->new_parent && clk->new_parent != clk->parent)

		__clk_set_parent(clk, clk->new_parent, clk->new_parent_index);



	if (clk->parent)

	if (clk->new_parent)

		best_parent_rate = clk->new_parent->rate;

	else if (clk->parent)

		best_parent_rate = clk->parent->rate;



	if (clk->ops->set_rate)

	if (clk->new_parent && clk->new_parent != clk->parent) {

		old_parent = __clk_set_parent_before(clk, clk->new_parent);



		if (clk->ops->set_rate_and_parent) {

			skip_set_rate = true;

			clk->ops->set_rate_and_parent(clk->hw, clk->new_rate,

					best_parent_rate,

					clk->new_parent_index);

		} else if (clk->ops->set_parent) {

			clk->ops->set_parent(clk->hw, clk->new_parent_index);

		}



		__clk_set_parent_after(clk, clk->new_parent, old_parent);

	}



	if (!skip_set_rate && clk->ops->set_rate)

		clk->ops->set_rate(clk->hw, clk->new_rate, best_parent_rate);



	if (clk->ops->recalc_rate)
@@ -1770,6 +1802,14 @@ int __clk_init(struct device *dev, struct clk *clk) 
		goto out;

	}



	if (clk->ops->set_rate_and_parent &&

			!(clk->ops->set_parent && clk->ops->set_rate)) {

		pr_warn("%s: %s must implement .set_parent & .set_rate\n",

				__func__, clk->name);

		ret = -EINVAL;

		goto out;

	}



	/* throw a WARN if any entries in parent_names are NULL */

	for (i = 0; i < clk->num_parents; i++)

		WARN(!clk->parent_names[i],

include/linux/clk-provider.h

+15 −0
Original line number Diff line number Diff line
@@ -116,6 +116,18 @@ struct clk_hw; 
 *		set then clock accuracy will be initialized to parent accuracy

 *		or 0 (perfect clock) if clock has no parent.

 *

 * @set_rate_and_parent: Change the rate and the parent of this clock. The

 *		requested rate is specified by the second argument, which

 *		should typically be the return of .round_rate call.  The

 *		third argument gives the parent rate which is likely helpful

 *		for most .set_rate_and_parent implementation. The fourth

 *		argument gives the parent index. This callback is optional (and

 *		unnecessary) for clocks with 0 or 1 parents as well as

 *		for clocks that can tolerate switching the rate and the parent

 *		separately via calls to .set_parent and .set_rate.

 *		Returns 0 on success, -EERROR otherwise.

 *

 *

 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow

 * implementations to split any work between atomic (enable) and sleepable

 * (prepare) contexts.  If enabling a clock requires code that might sleep,
@@ -147,6 +159,9 @@ struct clk_ops { 
	u8		(*get_parent)(struct clk_hw *hw);

	int		(*set_rate)(struct clk_hw *hw, unsigned long,

				    unsigned long);

	int		(*set_rate_and_parent)(struct clk_hw *hw,

				    unsigned long rate,

				    unsigned long parent_rate, u8 index);

	unsigned long	(*recalc_accuracy)(struct clk_hw *hw,

					   unsigned long parent_accuracy);

	void		(*init)(struct clk_hw *hw);

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