Commit 3f937cf3 authored by Heiko Stuebner's avatar Heiko Stuebner
Browse files

Revert "ARM: rockchip: fix undefined instruction of reset_ctrl_regs" 



This reverts commit b403125d.

As reported by Chris, both commits
        b403125d "ARM: rockchip: fix undefined instruction of reset_ctrl_regs"
        0ea001d3 "ARM: rockchip: disable dapswjdp during suspend"
actually fix the same issue and b403125d is the older one, which got
superseded by 0ea001d3. Therefore revert the obsolete one again.

Reported-by: default avatarChris Zhong <zyw@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 2a9fe3ca

arch/arm/mach-rockchip/pm.c

+0 −26
Original line number Diff line number Diff line
@@ -44,11 +44,9 @@ static void __iomem *rk3288_bootram_base; 
static phys_addr_t rk3288_bootram_phy;



static struct regmap *pmu_regmap;

static struct regmap *grf_regmap;

static struct regmap *sgrf_regmap;



static u32 rk3288_pmu_pwr_mode_con;

static u32 rk3288_grf_soc_con0;

static u32 rk3288_sgrf_soc_con0;



static inline u32 rk3288_l2_config(void)
@@ -72,25 +70,11 @@ static void rk3288_slp_mode_set(int level) 
{

	u32 mode_set, mode_set1;



	regmap_read(grf_regmap, RK3288_GRF_SOC_CON0, &rk3288_grf_soc_con0);



	regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);



	regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,

		    &rk3288_pmu_pwr_mode_con);



	/*

	 * We need set this bit GRF_FORCE_JTAG here, for the debug module,

	 * otherwise, it may become inaccessible after resume.

	 * This creates a potential security issue, as the sdmmc pins may

	 * accept jtag data for a short time during resume if no card is

	 * inserted.

	 * But this is of course also true for the regular boot, before we

	 * turn of the jtag/sdmmc autodetect.

	 */

	regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, GRF_FORCE_JTAG |

		     GRF_FORCE_JTAG_WRITE);



	/*

	 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR

	 * PCLK_WDT_GATE - disable WDT during suspend.
@@ -151,9 +135,6 @@ static void rk3288_slp_mode_set_resume(void) 
	regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,

		     rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE

		     | SGRF_FAST_BOOT_EN_WRITE);



	regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, rk3288_grf_soc_con0 |

		     GRF_FORCE_JTAG_WRITE);

}



static int rockchip_lpmode_enter(unsigned long arg)
@@ -212,13 +193,6 @@ static int rk3288_suspend_init(struct device_node *np) 
		return PTR_ERR(pmu_regmap);

	}



	grf_regmap = syscon_regmap_lookup_by_compatible(

				"rockchip,rk3288-grf");

	if (IS_ERR(grf_regmap)) {

		pr_err("%s: could not find grf regmap\n", __func__);

		return PTR_ERR(pmu_regmap);

	}



	sram_np = of_find_compatible_node(NULL, NULL,

					  "rockchip,rk3288-pmu-sram");

	if (!sram_np) {

arch/arm/mach-rockchip/pm.h

+0 −4
Original line number Diff line number Diff line
@@ -48,10 +48,6 @@ static inline void rockchip_suspend_init(void) 
#define RK3288_PMU_WAKEUP_RST_CLR_CNT	0x44

#define RK3288_PMU_PWRMODE_CON1		0x90



#define RK3288_GRF_SOC_CON0		0x244

#define GRF_FORCE_JTAG			BIT(12)

#define GRF_FORCE_JTAG_WRITE		BIT(28)



#define RK3288_SGRF_SOC_CON0		(0x0000)

#define RK3288_SGRF_FAST_BOOT_ADDR	(0x0120)

#define SGRF_PCLK_WDT_GATE		BIT(6)

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