Commit 3f8a2b74 authored by David S. Miller's avatar David S. Miller
Browse files

Merge tag 'linux-can-next-for-3.18-20140820' of git://gitorious.org/linux-can/linux-can-next



Marc Kleine-Budde says:

====================
pull-request: can-next 2014-08-20

this is a pull request of 10 patches for net-next/master.

There is one patch by Wolfram Sang to clean up the build system.
Two patches by Stefan Agner that add vf610 support to the flexcan
driver. Dong Aisheng add support for bosch's m_can core, which is found
in the new freescale ARM SoCs. Sergei Shtylyov improves the rcar_can
driver by supporting all input clocks and adding device tree support.
The next patch is a small cleanup for the bit rate calculation function
by Lad, Prabhakar. And finally a patch by Himangi Saraogi, which
converts the mcp251x driver to use dmam_alloc_coherent.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 13322f2e 3a73aeff
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Bosch MCAN controller Device Tree Bindings
-------------------------------------------------

Required properties:
- compatible		: Should be "bosch,m_can" for M_CAN controllers
- reg			: physical base address and size of the M_CAN
			  registers map and Message RAM
- reg-names		: Should be "m_can" and "message_ram"
- interrupts		: Should be the interrupt number of M_CAN interrupt
			  line 0 and line 1, could be same if sharing
			  the same interrupt.
- interrupt-names	: Should contain "int0" and "int1"
- clocks		: Clocks used by controller, should be host clock
			  and CAN clock.
- clock-names		: Should contain "hclk" and "cclk"
- pinctrl-<n>		: Pinctrl states as described in bindings/pinctrl/pinctrl-bindings.txt
- pinctrl-names 	: Names corresponding to the numbered pinctrl states
- bosch,mram-cfg	: Message RAM configuration data.
			  Multiple M_CAN instances can share the same Message
			  RAM and each element(e.g Rx FIFO or Tx Buffer and etc)
			  number in Message RAM is also configurable,
			  so this property is telling driver how the shared or
			  private Message RAM are used by this M_CAN controller.

			  The format should be as follows:
			  <offset sidf_elems xidf_elems rxf0_elems rxf1_elems
			   rxb_elems txe_elems txb_elems>
			  The 'offset' is an address offset of the Message RAM
			  where the following elements start from. This is
			  usually set to 0x0 if you're using a private Message
			  RAM. The remain cells are used to specify how many
			  elements are used for each FIFO/Buffer.

			  M_CAN includes the following elements according to user manual:
			  11-bit Filter	0-128 elements / 0-128 words
			  29-bit Filter	0-64 elements / 0-128 words
			  Rx FIFO 0	0-64 elements / 0-1152 words
			  Rx FIFO 1	0-64 elements / 0-1152 words
			  Rx Buffers	0-64 elements / 0-1152 words
			  Tx Event FIFO	0-32 elements / 0-64 words
			  Tx Buffers	0-32 elements / 0-576 words

			  Please refer to 2.4.1 Message RAM Configuration in
			  Bosch M_CAN user manual for details.

Example:
SoC dtsi:
m_can1: can@020e8000 {
	compatible = "bosch,m_can";
	reg = <0x020e8000 0x4000>, <0x02298000 0x4000>;
	reg-names = "m_can", "message_ram";
	interrupts = <0 114 0x04>,
		     <0 114 0x04>;
	interrupt-names = "int0", "int1";
	clocks = <&clks IMX6SX_CLK_CANFD>,
		 <&clks IMX6SX_CLK_CANFD>;
	clock-names = "hclk", "cclk";
	bosch,mram-cfg = <0x0 0 0 32 0 0 0 1>;
	status = "disabled";
};

Board dts:
&m_can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_m_can1>;
	status = "enabled";
};
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Renesas R-Car CAN controller Device Tree Bindings
-------------------------------------------------

Required properties:
- compatible: "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC.
	      "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC.
	      "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC.
	      "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC.
- reg: physical base address and size of the R-Car CAN register map.
- interrupts: interrupt specifier for the sole interrupt.
- clocks: phandles and clock specifiers for 3 CAN clock inputs.
- clock-names: 3 clock input name strings: "clkp1", "clkp2", "can_clk".
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must be "default".

Optional properties:
- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are:
			    <0x0> (default) : Peripheral clock (clkp1)
			    <0x1> : Peripheral clock (clkp2)
			    <0x3> : Externally input clock

Example
-------

SoC common .dtsi file:

	can0: can@e6e80000 {
		compatible = "renesas,can-r8a7791";
		reg = <0 0xe6e80000 0 0x1000>;
		interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
			 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
		clock-names = "clkp1", "clkp2", "can_clk";
		status = "disabled";
	};

Board specific .dts file:

&can0 {
	pinctrl-0 = <&can0_pins>;
	pinctrl-names = "default";
	status = "okay";
};
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@@ -143,6 +143,8 @@ source "drivers/net/can/sja1000/Kconfig"

source "drivers/net/can/c_can/Kconfig"

source "drivers/net/can/m_can/Kconfig"

source "drivers/net/can/cc770/Kconfig"

source "drivers/net/can/spi/Kconfig"
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@@ -17,6 +17,7 @@ obj-y += softing/
obj-$(CONFIG_CAN_SJA1000)	+= sja1000/
obj-$(CONFIG_CAN_MSCAN)		+= mscan/
obj-$(CONFIG_CAN_C_CAN)		+= c_can/
obj-$(CONFIG_CAN_M_CAN)		+= m_can/
obj-$(CONFIG_CAN_CC770)		+= cc770/
obj-$(CONFIG_CAN_AT91)		+= at91_can.o
obj-$(CONFIG_CAN_TI_HECC)	+= ti_hecc.o
@@ -28,4 +29,4 @@ obj-$(CONFIG_CAN_GRCAN) += grcan.o
obj-$(CONFIG_CAN_RCAR)		+= rcar_can.o
obj-$(CONFIG_CAN_XILINXCAN)	+= xilinx_can.o

ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
subdir-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
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@@ -5,5 +5,3 @@
obj-$(CONFIG_CAN_C_CAN) += c_can.o
obj-$(CONFIG_CAN_C_CAN_PLATFORM) += c_can_platform.o
obj-$(CONFIG_CAN_C_CAN_PCI) += c_can_pci.o

ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
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