Commit 3f3fef5f authored by Ching-Te Ku's avatar Ching-Te Ku Committed by Kalle Valo
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rtw88: coex: fixed some wrong register definition and setting 



Some register definition and bit definition were incorrect.
e.g. REG_BT_COEX_V2 should be word alignment to meet the coding style.
e.g. set REG_BT_TDMA_TIME[5:0]=0x5,
But the original is to set REG_BT_TDMA_TIME[7:0]=0x5.
This will cause unexpected hardware behavior.

Signed-off-by: default avatarChing-Te Ku <ku920601@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/20201109085909.9143-2-pkshih@realtek.com
parent dd90fc46

drivers/net/wireless/realtek/rtw88/reg.h

+4 −3
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ 
#define REG_GPIO_MUXCFG		0x0040

#define BIT_FSPI_EN		BIT(19)

#define BIT_EN_SIC		BIT(12)

#define BIT_BT_AOD_GPIO3	BIT(9)



#define BIT_PO_BT_PTA_PINS	BIT(9)

#define BIT_BT_PTA_EN		BIT(5)

#define BIT_WLRFE_4_5_EN	BIT(2)
@@ -463,11 +463,12 @@ 
#define REG_BT_COEX_TABLE_H3	0x06CF

#define REG_BBPSF_CTRL		0x06DC



#define REG_BT_COEX_V2		0x0763

#define BIT_GNT_BT_POLARITY	BIT(4)

#define REG_BT_COEX_V2		0x0762

#define BIT_GNT_BT_POLARITY	BIT(12)

#define BIT_LTE_COEX_EN		BIT(7)

#define REG_BT_STAT_CTRL	0x0778

#define REG_BT_TDMA_TIME	0x0790

#define BIT_MASK_SAMPLE_RATE	GENMASK(5, 0)

#define REG_LTR_IDLE_LATENCY	0x0798

#define REG_LTR_ACTIVE_LATENCY	0x079C

#define REG_LTR_CTRL_BASIC	0x07A4

drivers/net/wireless/realtek/rtw88/rtw8723d.c

+2 −2
Original line number Diff line number Diff line
@@ -1506,14 +1506,14 @@ static void rtw8723d_coex_cfg_init(struct rtw_dev *rtwdev) 


	/* BT report packet sample rate	 */

	/* 0x790[5:0]=0x5 */

	rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);

	rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);



	/* enable BT counter statistics */

	rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);



	/* enable PTA (3-wire function form BT side) */

	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);

	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);

	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);



	/* enable PTA (tx/rx signal form WiFi side) */

	rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);

drivers/net/wireless/realtek/rtw88/rtw8821c.c

+1 −2
Original line number Diff line number Diff line
@@ -656,8 +656,7 @@ static void rtw8821c_coex_cfg_init(struct rtw_dev *rtwdev) 
	rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);



	/* BT report packet sample rate */

	rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, SAMPLE_RATE_MASK,

			SAMPLE_RATE);

	rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);



	/* enable BT counter statistics */

	rtw_write8(rtwdev, REG_BT_STAT_CTRL, BT_CNT_ENABLE);

drivers/net/wireless/realtek/rtw88/rtw8821c.h

+0 −2
Original line number Diff line number Diff line
@@ -231,8 +231,6 @@ _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) 
#define REG_IQKFAILMSK	0x1bf0

#define BIT_MASK_R_RFE_SEL_15	GENMASK(31, 28)

#define BIT_SDIO_INT BIT(18)

#define SAMPLE_RATE_MASK GENMASK(5, 0)

#define SAMPLE_RATE	0x5

#define BT_CNT_ENABLE	0x1

#define BIT_BCN_QUEUE	BIT(3)

#define BCN_PRI_EN	0x1

drivers/net/wireless/realtek/rtw88/rtw8822b.c

+3 −3
Original line number Diff line number Diff line
@@ -1120,21 +1120,21 @@ static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev) 


	/* BT report packet sample rate */

	/* 0x790[5:0]=0x5 */

	rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05);

	rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);



	/* enable BT counter statistics */

	rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);



	/* enable PTA (3-wire function form BT side) */

	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);

	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3);

	rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);



	/* enable PTA (tx/rx signal form WiFi side) */

	rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);

	/* wl tx signal to PTA not case EDCCA */

	rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);

	/* GNT_BT=1 while select both */

	rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);

	rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);

}



static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev,

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