Commit 3f26ab58 authored by Will Deacon's avatar Will Deacon Committed by Marc Zyngier
Browse files

KVM: arm64: Remove unused page-table code 



Now that KVM is using the generic page-table code to manage the guest
stage-2 page-tables, we can remove a bunch of unused macros, #defines
and static inline functions from the old implementation.

Signed-off-by: default avatarWill Deacon <will@kernel.org>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Reviewed-by: default avatarGavin Shan <gshan@redhat.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Quentin Perret <qperret@google.com>
Link: https://lore.kernel.org/r/20200911132529.19844-20-will@kernel.org
parent 063deeb1

arch/arm64/include/asm/kvm_mmu.h

+0 −171
Original line number Diff line number Diff line
@@ -107,12 +107,6 @@ static __always_inline unsigned long __kern_hyp_va(unsigned long v) 
#define kvm_phys_size(kvm)		(_AC(1, ULL) << kvm_phys_shift(kvm))

#define kvm_phys_mask(kvm)		(kvm_phys_size(kvm) - _AC(1, ULL))



static inline bool kvm_page_empty(void *ptr)

{

	struct page *ptr_page = virt_to_page(ptr);

	return page_count(ptr_page) == 1;

}



#include <asm/kvm_pgtable.h>

#include <asm/stage2_pgtable.h>
@@ -135,123 +129,6 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu); 
phys_addr_t kvm_mmu_get_httbr(void);

phys_addr_t kvm_get_idmap_vector(void);

int kvm_mmu_init(void);

#define kvm_mk_pmd(ptep)					\

	__pmd(__phys_to_pmd_val(__pa(ptep)) | PMD_TYPE_TABLE)

#define kvm_mk_pud(pmdp)					\

	__pud(__phys_to_pud_val(__pa(pmdp)) | PMD_TYPE_TABLE)

#define kvm_mk_p4d(pmdp)					\

	__p4d(__phys_to_p4d_val(__pa(pmdp)) | PUD_TYPE_TABLE)



#define kvm_set_pud(pudp, pud)		set_pud(pudp, pud)



#define kvm_pfn_pte(pfn, prot)		pfn_pte(pfn, prot)

#define kvm_pfn_pmd(pfn, prot)		pfn_pmd(pfn, prot)

#define kvm_pfn_pud(pfn, prot)		pfn_pud(pfn, prot)



#define kvm_pud_pfn(pud)		pud_pfn(pud)



#define kvm_pmd_mkhuge(pmd)		pmd_mkhuge(pmd)

#define kvm_pud_mkhuge(pud)		pud_mkhuge(pud)



static inline pte_t kvm_s2pte_mkwrite(pte_t pte)

{

	pte_val(pte) |= PTE_S2_RDWR;

	return pte;

}



static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd)

{

	pmd_val(pmd) |= PMD_S2_RDWR;

	return pmd;

}



static inline pud_t kvm_s2pud_mkwrite(pud_t pud)

{

	pud_val(pud) |= PUD_S2_RDWR;

	return pud;

}



static inline pte_t kvm_s2pte_mkexec(pte_t pte)

{

	pte_val(pte) &= ~PTE_S2_XN;

	return pte;

}



static inline pmd_t kvm_s2pmd_mkexec(pmd_t pmd)

{

	pmd_val(pmd) &= ~PMD_S2_XN;

	return pmd;

}



static inline pud_t kvm_s2pud_mkexec(pud_t pud)

{

	pud_val(pud) &= ~PUD_S2_XN;

	return pud;

}



static inline void kvm_set_s2pte_readonly(pte_t *ptep)

{

	pteval_t old_pteval, pteval;



	pteval = READ_ONCE(pte_val(*ptep));

	do {

		old_pteval = pteval;

		pteval &= ~PTE_S2_RDWR;

		pteval |= PTE_S2_RDONLY;

		pteval = cmpxchg_relaxed(&pte_val(*ptep), old_pteval, pteval);

	} while (pteval != old_pteval);

}



static inline bool kvm_s2pte_readonly(pte_t *ptep)

{

	return (READ_ONCE(pte_val(*ptep)) & PTE_S2_RDWR) == PTE_S2_RDONLY;

}



static inline bool kvm_s2pte_exec(pte_t *ptep)

{

	return !(READ_ONCE(pte_val(*ptep)) & PTE_S2_XN);

}



static inline void kvm_set_s2pmd_readonly(pmd_t *pmdp)

{

	kvm_set_s2pte_readonly((pte_t *)pmdp);

}



static inline bool kvm_s2pmd_readonly(pmd_t *pmdp)

{

	return kvm_s2pte_readonly((pte_t *)pmdp);

}



static inline bool kvm_s2pmd_exec(pmd_t *pmdp)

{

	return !(READ_ONCE(pmd_val(*pmdp)) & PMD_S2_XN);

}



static inline void kvm_set_s2pud_readonly(pud_t *pudp)

{

	kvm_set_s2pte_readonly((pte_t *)pudp);

}



static inline bool kvm_s2pud_readonly(pud_t *pudp)

{

	return kvm_s2pte_readonly((pte_t *)pudp);

}



static inline bool kvm_s2pud_exec(pud_t *pudp)

{

	return !(READ_ONCE(pud_val(*pudp)) & PUD_S2_XN);

}



static inline pud_t kvm_s2pud_mkyoung(pud_t pud)

{

	return pud_mkyoung(pud);

}



static inline bool kvm_s2pud_young(pud_t pud)

{

	return pud_young(pud);

}





struct kvm;
@@ -293,30 +170,6 @@ static inline void __invalidate_icache_guest_page(kvm_pfn_t pfn, 
	}

}



static inline void __kvm_flush_dcache_pte(pte_t pte)

{

	if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {

		struct page *page = pte_page(pte);

		kvm_flush_dcache_to_poc(page_address(page), PAGE_SIZE);

	}

}



static inline void __kvm_flush_dcache_pmd(pmd_t pmd)

{

	if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {

		struct page *page = pmd_page(pmd);

		kvm_flush_dcache_to_poc(page_address(page), PMD_SIZE);

	}

}



static inline void __kvm_flush_dcache_pud(pud_t pud)

{

	if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB)) {

		struct page *page = pud_page(pud);

		kvm_flush_dcache_to_poc(page_address(page), PUD_SIZE);

	}

}



void kvm_set_way_flush(struct kvm_vcpu *vcpu);

void kvm_toggle_cache(struct kvm_vcpu *vcpu, bool was_enabled);
@@ -477,30 +330,6 @@ static inline int hyp_map_aux_data(void) 


#define kvm_phys_to_vttbr(addr)		phys_to_ttbr(addr)



/*

 * Get the magic number 'x' for VTTBR:BADDR of this KVM instance.

 * With v8.2 LVA extensions, 'x' should be a minimum of 6 with

 * 52bit IPS.

 */

static inline int arm64_vttbr_x(u32 ipa_shift, u32 levels)

{

	int x = ARM64_VTTBR_X(ipa_shift, levels);



	return (IS_ENABLED(CONFIG_ARM64_PA_BITS_52) && x < 6) ? 6 : x;

}



static inline u64 vttbr_baddr_mask(u32 ipa_shift, u32 levels)

{

	unsigned int x = arm64_vttbr_x(ipa_shift, levels);



	return GENMASK_ULL(PHYS_MASK_SHIFT - 1, x);

}



static inline u64 kvm_vttbr_baddr_mask(struct kvm *kvm)

{

	return vttbr_baddr_mask(kvm_phys_shift(kvm), kvm_stage2_levels(kvm));

}



static __always_inline u64 kvm_get_vttbr(struct kvm_s2_mmu *mmu)

{

	struct kvm_vmid *vmid = &mmu->vmid;

arch/arm64/include/asm/pgtable-hwdef.h

+0 −18
Original line number Diff line number Diff line
@@ -156,7 +156,6 @@ 
#define PTE_CONT		(_AT(pteval_t, 1) << 52)	/* Contiguous range */

#define PTE_PXN			(_AT(pteval_t, 1) << 53)	/* Privileged XN */

#define PTE_UXN			(_AT(pteval_t, 1) << 54)	/* User XN */

#define PTE_HYP_XN		(_AT(pteval_t, 1) << 54)	/* HYP XN */



#define PTE_ADDR_LOW		(((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)

#ifdef CONFIG_ARM64_PA_BITS_52
@@ -172,23 +171,6 @@ 
#define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)

#define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)



/*

 * 2nd stage PTE definitions

 */

#define PTE_S2_RDONLY		(_AT(pteval_t, 1) << 6)   /* HAP[2:1] */

#define PTE_S2_RDWR		(_AT(pteval_t, 3) << 6)   /* HAP[2:1] */

#define PTE_S2_XN		(_AT(pteval_t, 2) << 53)  /* XN[1:0] */

#define PTE_S2_SW_RESVD		(_AT(pteval_t, 15) << 55) /* Reserved for SW */



#define PMD_S2_RDONLY		(_AT(pmdval_t, 1) << 6)   /* HAP[2:1] */

#define PMD_S2_RDWR		(_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */

#define PMD_S2_XN		(_AT(pmdval_t, 2) << 53)  /* XN[1:0] */

#define PMD_S2_SW_RESVD		(_AT(pmdval_t, 15) << 55) /* Reserved for SW */



#define PUD_S2_RDONLY		(_AT(pudval_t, 1) << 6)   /* HAP[2:1] */

#define PUD_S2_RDWR		(_AT(pudval_t, 3) << 6)   /* HAP[2:1] */

#define PUD_S2_XN		(_AT(pudval_t, 2) << 53)  /* XN[1:0] */



/*

 * Memory Attribute override for Stage-2 (MemAttr[3:0])

 */

arch/arm64/include/asm/pgtable-prot.h

+0 −13
Original line number Diff line number Diff line
@@ -73,19 +73,6 @@ extern bool arm64_use_ng_mappings; 
		__val;							\

	 })



#define PAGE_S2_XN							\

	({								\

		u64 __val;						\

		if (cpus_have_const_cap(ARM64_HAS_CACHE_DIC))		\

			__val = 0;					\

		else							\

			__val = PTE_S2_XN;				\

		__val;							\

	})



#define PAGE_S2			__pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDONLY | PAGE_S2_XN)

#define PAGE_S2_DEVICE		__pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN)



#define PAGE_NONE		__pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)

/* shared+writable pages are clean by default, hence PTE_RDONLY|PTE_WRITE */

#define PAGE_SHARED		__pgprot(_PAGE_DEFAULT | PTE_USER | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)

arch/arm64/include/asm/stage2_pgtable.h

+0 −215
Original line number Diff line number Diff line
@@ -8,7 +8,6 @@ 
#ifndef __ARM64_S2_PGTABLE_H_

#define __ARM64_S2_PGTABLE_H_



#include <linux/hugetlb.h>

#include <linux/pgtable.h>



/*
@@ -36,21 +35,6 @@ 
#define stage2_pgdir_size(kvm)		(1ULL << stage2_pgdir_shift(kvm))

#define stage2_pgdir_mask(kvm)		~(stage2_pgdir_size(kvm) - 1)



/*

 * The number of PTRS across all concatenated stage2 tables given by the

 * number of bits resolved at the initial level.

 * If we force more levels than necessary, we may have (stage2_pgdir_shift > IPA),

 * in which case, stage2_pgd_ptrs will have one entry.

 */

#define pgd_ptrs_shift(ipa, pgdir_shift)	\

	((ipa) > (pgdir_shift) ? ((ipa) - (pgdir_shift)) : 0)

#define __s2_pgd_ptrs(ipa, lvls)		\

	(1 << (pgd_ptrs_shift((ipa), pt_levels_pgdir_shift(lvls))))

#define __s2_pgd_size(ipa, lvls)	(__s2_pgd_ptrs((ipa), (lvls)) * sizeof(pgd_t))



#define stage2_pgd_ptrs(kvm)		__s2_pgd_ptrs(kvm_phys_shift(kvm), kvm_stage2_levels(kvm))

#define stage2_pgd_size(kvm)		__s2_pgd_size(kvm_phys_shift(kvm), kvm_stage2_levels(kvm))



/*

 * kvm_mmmu_cache_min_pages() is the number of pages required to install

 * a stage-2 translation. We pre-allocate the entry level page table at
@@ -58,196 +42,6 @@ 
 */

#define kvm_mmu_cache_min_pages(kvm)	(kvm_stage2_levels(kvm) - 1)



/* Stage2 PUD definitions when the level is present */

static inline bool kvm_stage2_has_pud(struct kvm *kvm)

{

	return (CONFIG_PGTABLE_LEVELS > 3) && (kvm_stage2_levels(kvm) > 3);

}



#define S2_PUD_SHIFT			ARM64_HW_PGTABLE_LEVEL_SHIFT(1)

#define S2_PUD_SIZE			(1UL << S2_PUD_SHIFT)

#define S2_PUD_MASK			(~(S2_PUD_SIZE - 1))



#define stage2_pgd_none(kvm, pgd)		pgd_none(pgd)

#define stage2_pgd_clear(kvm, pgd)		pgd_clear(pgd)

#define stage2_pgd_present(kvm, pgd)		pgd_present(pgd)

#define stage2_pgd_populate(kvm, pgd, p4d)	pgd_populate(NULL, pgd, p4d)



static inline p4d_t *stage2_p4d_offset(struct kvm *kvm,

				       pgd_t *pgd, unsigned long address)

{

	return p4d_offset(pgd, address);

}



static inline void stage2_p4d_free(struct kvm *kvm, p4d_t *p4d)

{

}



static inline bool stage2_p4d_table_empty(struct kvm *kvm, p4d_t *p4dp)

{

	return false;

}



static inline phys_addr_t stage2_p4d_addr_end(struct kvm *kvm,

					      phys_addr_t addr, phys_addr_t end)

{

	return end;

}



static inline bool stage2_p4d_none(struct kvm *kvm, p4d_t p4d)

{

	if (kvm_stage2_has_pud(kvm))

		return p4d_none(p4d);

	else

		return 0;

}



static inline void stage2_p4d_clear(struct kvm *kvm, p4d_t *p4dp)

{

	if (kvm_stage2_has_pud(kvm))

		p4d_clear(p4dp);

}



static inline bool stage2_p4d_present(struct kvm *kvm, p4d_t p4d)

{

	if (kvm_stage2_has_pud(kvm))

		return p4d_present(p4d);

	else

		return 1;

}



static inline void stage2_p4d_populate(struct kvm *kvm, p4d_t *p4d, pud_t *pud)

{

	if (kvm_stage2_has_pud(kvm))

		p4d_populate(NULL, p4d, pud);

}



static inline pud_t *stage2_pud_offset(struct kvm *kvm,

				       p4d_t *p4d, unsigned long address)

{

	if (kvm_stage2_has_pud(kvm))

		return pud_offset(p4d, address);

	else

		return (pud_t *)p4d;

}



static inline void stage2_pud_free(struct kvm *kvm, pud_t *pud)

{

	if (kvm_stage2_has_pud(kvm))

		free_page((unsigned long)pud);

}



static inline bool stage2_pud_table_empty(struct kvm *kvm, pud_t *pudp)

{

	if (kvm_stage2_has_pud(kvm))

		return kvm_page_empty(pudp);

	else

		return false;

}



static inline phys_addr_t

stage2_pud_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end)

{

	if (kvm_stage2_has_pud(kvm)) {

		phys_addr_t boundary = (addr + S2_PUD_SIZE) & S2_PUD_MASK;



		return (boundary - 1 < end - 1) ? boundary : end;

	} else {

		return end;

	}

}



/* Stage2 PMD definitions when the level is present */

static inline bool kvm_stage2_has_pmd(struct kvm *kvm)

{

	return (CONFIG_PGTABLE_LEVELS > 2) && (kvm_stage2_levels(kvm) > 2);

}



#define S2_PMD_SHIFT			ARM64_HW_PGTABLE_LEVEL_SHIFT(2)

#define S2_PMD_SIZE			(1UL << S2_PMD_SHIFT)

#define S2_PMD_MASK			(~(S2_PMD_SIZE - 1))



static inline bool stage2_pud_none(struct kvm *kvm, pud_t pud)

{

	if (kvm_stage2_has_pmd(kvm))

		return pud_none(pud);

	else

		return 0;

}



static inline void stage2_pud_clear(struct kvm *kvm, pud_t *pud)

{

	if (kvm_stage2_has_pmd(kvm))

		pud_clear(pud);

}



static inline bool stage2_pud_present(struct kvm *kvm, pud_t pud)

{

	if (kvm_stage2_has_pmd(kvm))

		return pud_present(pud);

	else

		return 1;

}



static inline void stage2_pud_populate(struct kvm *kvm, pud_t *pud, pmd_t *pmd)

{

	if (kvm_stage2_has_pmd(kvm))

		pud_populate(NULL, pud, pmd);

}



static inline pmd_t *stage2_pmd_offset(struct kvm *kvm,

				       pud_t *pud, unsigned long address)

{

	if (kvm_stage2_has_pmd(kvm))

		return pmd_offset(pud, address);

	else

		return (pmd_t *)pud;

}



static inline void stage2_pmd_free(struct kvm *kvm, pmd_t *pmd)

{

	if (kvm_stage2_has_pmd(kvm))

		free_page((unsigned long)pmd);

}



static inline bool stage2_pud_huge(struct kvm *kvm, pud_t pud)

{

	if (kvm_stage2_has_pmd(kvm))

		return pud_huge(pud);

	else

		return 0;

}



static inline bool stage2_pmd_table_empty(struct kvm *kvm, pmd_t *pmdp)

{

	if (kvm_stage2_has_pmd(kvm))

		return kvm_page_empty(pmdp);

	else

		return 0;

}



static inline phys_addr_t

stage2_pmd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end)

{

	if (kvm_stage2_has_pmd(kvm)) {

		phys_addr_t boundary = (addr + S2_PMD_SIZE) & S2_PMD_MASK;



		return (boundary - 1 < end - 1) ? boundary : end;

	} else {

		return end;

	}

}



static inline bool stage2_pte_table_empty(struct kvm *kvm, pte_t *ptep)

{

	return kvm_page_empty(ptep);

}



static inline unsigned long stage2_pgd_index(struct kvm *kvm, phys_addr_t addr)

{

	return (((addr) >> stage2_pgdir_shift(kvm)) & (stage2_pgd_ptrs(kvm) - 1));

}



static inline phys_addr_t

stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end)

{
@@ -256,13 +50,4 @@ stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) 
	return (boundary - 1 < end - 1) ? boundary : end;

}



/*

 * Level values for the ARMv8.4-TTL extension, mapping PUD/PMD/PTE and

 * the architectural page-table level.

 */

#define S2_NO_LEVEL_HINT	0

#define S2_PUD_LEVEL		1

#define S2_PMD_LEVEL		2

#define S2_PTE_LEVEL		3



#endif	/* __ARM64_S2_PGTABLE_H_ */

arch/arm64/kvm/mmu.c

+0 −755

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