Commit 3ecb3b79 authored by Mauro Rossi's avatar Mauro Rossi Committed by Alex Deucher
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drm/amd/display: dc/clk_mgr: add support for SI parts (v2) 



(v1) Changelog

[Why]
After commit c69dd2d0 "drm/amd/display: Refactor clk_mgr functions"
dc/clk_mgr requires these changes to add SI parts support
Necessary to avoid hitting default: ASSERT(0); /* Unknown Asic */
that would cause kernel freeze

[How]
Add case statement for FAMILY_SI chipsets

(v2) Changelog

[Why]
DCE6 has no DPREFCLK_CNTL register

[How]
Add DCE6 specific macros definitions for CLK registers and masks
Add DCE6 specific dce60/dce60_clk_mgr.c for DCE6 customization
Code style: reuse all the public functions in dce100/dce_clk_mgr.h header
Code style: use dce60_* static functions as per other DCE implementations
Add dce60_get_dp_ref_freq_khz() w/o using DPREFCLK_CNTL register
Use dce60_get_dp_ref_freq_khz() function in dce60_funcs
Add DCE6 specific dce60_clk_mgr_construct
dc/clk_mgr/dce_clk_mgr.c: use dce60_clk_mgr_construct for FAMILY_SI chipsets
Add Makefile rules for dce60_clk_mgr.o target conditional to CONFIG_DRM_AMD_DC_SI

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarMauro Rossi <issor.oruam@gmail.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 55e56389

drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile

+11 −0
Original line number Diff line number Diff line
@@ -30,6 +30,17 @@ AMD_DAL_CLK_MGR = $(addprefix $(AMDDALPATH)/dc/clk_mgr/,$(CLK_MGR)) 
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR)





ifdef CONFIG_DRM_AMD_DC_SI

###############################################################################

# DCE 60

###############################################################################

CLK_MGR_DCE60 = dce60_clk_mgr.o



AMD_DAL_CLK_MGR_DCE60 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce60/,$(CLK_MGR_DCE60))



AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCE60)

endif



###############################################################################

# DCE 100 and DCE8x

###############################################################################

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+6 −0
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ 
#include "dce110/dce110_clk_mgr.h"

#include "dce112/dce112_clk_mgr.h"

#include "dce120/dce120_clk_mgr.h"

#include "dce60/dce60_clk_mgr.h"

#include "dcn10/rv1_clk_mgr.h"

#include "dcn10/rv2_clk_mgr.h"

#include "dcn20/dcn20_clk_mgr.h"
@@ -123,6 +124,11 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p 
	}



	switch (asic_id.chip_family) {

#if defined(CONFIG_DRM_AMD_DC_SI)

	case FAMILY_SI:

		dce60_clk_mgr_construct(ctx, clk_mgr);

		break;

#endif

	case FAMILY_CI:

	case FAMILY_KV:

		dce_clk_mgr_construct(ctx, clk_mgr);

drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c

0 → 100644
+174 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */





#include "dccg.h"

#include "clk_mgr_internal.h"

#include "dce100/dce_clk_mgr.h"

#include "dce110/dce110_clk_mgr.h"

#include "dce60_clk_mgr.h"

#include "reg_helper.h"

#include "dmcu.h"

#include "core_types.h"

#include "dal_asic_id.h"



/*

 * Currently the register shifts and masks in this file are used for dce60

 * which has no DPREFCLK_CNTL register

 * TODO: remove this when DENTIST_DISPCLK_CNTL

 * is moved to dccg, where it belongs

 */

#include "dce/dce_6_0_d.h"

#include "dce/dce_6_0_sh_mask.h"



#define REG(reg) \

	(clk_mgr->regs->reg)



#undef FN

#define FN(reg_name, field_name) \

	clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name



/* set register offset */

#define SR(reg_name)\

	.reg_name = mm ## reg_name



static const struct clk_mgr_registers disp_clk_regs = {

		CLK_COMMON_REG_LIST_DCE60_BASE()

};



static const struct clk_mgr_shift disp_clk_shift = {

		CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(__SHIFT)

};



static const struct clk_mgr_mask disp_clk_mask = {

		CLK_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(_MASK)

};





/* Max clock values for each state indexed by "enum clocks_state": */

static const struct state_dependent_clocks dce60_max_clks_by_state[] = {

/* ClocksStateInvalid - should not be used */

{ .display_clk_khz = 0, .pixel_clk_khz = 0 },

/* ClocksStateUltraLow - not expected to be used for DCE 6.0 */

{ .display_clk_khz = 0, .pixel_clk_khz = 0 },

/* ClocksStateLow */

{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},

/* ClocksStateNominal */

{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },

/* ClocksStatePerformance */

{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };



int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)

{

	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	int dprefclk_wdivider;

	int dp_ref_clk_khz;

	int target_div;



	/* DCE6 has no DPREFCLK_CNTL to read DP Reference Clock source */



	/* Read the mmDENTIST_DISPCLK_CNTL to get the currently

	 * programmed DID DENTIST_DPREFCLK_WDIVIDER*/

	REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);



	/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/

	target_div = dentist_get_divider_from_did(dprefclk_wdivider);



	/* Calculate the current DFS clock, in kHz.*/

	dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR

		* clk_mgr->base.dentist_vco_freq_khz) / target_div;



	return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);

}



static void dce60_pplib_apply_display_requirements(

	struct dc *dc,

	struct dc_state *context)

{

	struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;



	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);



	dce110_fill_display_configs(context, pp_display_cfg);



	if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) !=  0)

		dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);

}



static void dce60_update_clocks(struct clk_mgr *clk_mgr_base,

			struct dc_state *context,

			bool safe_to_lower)

{

	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);

	struct dm_pp_power_level_change_request level_change_req;

	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;



	/*TODO: W/A for dal3 linux, investigate why this works */

	if (!clk_mgr_dce->dfs_bypass_active)

		patched_disp_clk = patched_disp_clk * 115 / 100;



	level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);

	/* get max clock state from PPLIB */

	if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower)

			|| level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) {

		if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req))

			clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;

	}



	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {

		patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk);

		clk_mgr_base->clks.dispclk_khz = patched_disp_clk;

	}

	dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);

}

















static struct clk_mgr_funcs dce60_funcs = {

	.get_dp_ref_clk_frequency = dce60_get_dp_ref_freq_khz,

	.update_clocks = dce60_update_clocks

};



void dce60_clk_mgr_construct(

		struct dc_context *ctx,

		struct clk_mgr_internal *clk_mgr)

{

	dce_clk_mgr_construct(ctx, clk_mgr);



	memcpy(clk_mgr->max_clks_by_state,

		dce60_max_clks_by_state,

		sizeof(dce60_max_clks_by_state));



	clk_mgr->regs = &disp_clk_regs;

	clk_mgr->clk_mgr_shift = &disp_clk_shift;

	clk_mgr->clk_mgr_mask = &disp_clk_mask;

	clk_mgr->base.funcs = &dce60_funcs;

}

drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.h

0 → 100644
+36 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2020 Mauro Rossi <issor.oruam@gmail.com>

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */





#ifndef DAL_DC_DCE_DCE60_CLK_MGR_H_

#define DAL_DC_DCE_DCE60_CLK_MGR_H_



#include "dc.h"



void dce60_clk_mgr_construct(

		struct dc_context *ctx,

		struct clk_mgr_internal *clk_mgr_dce);



#endif /* DAL_DC_DCE_DCE60_CLK_MGR_H_ */

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