Commit 3ebab625 authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amd: the data retured from PRT is expected to be 0 



The dummy page for returning from PRT resides inside system memory,
need set system flag bit in VM_L2_CNTL.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b1fa87a4

drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.c

+2 −1
Original line number Diff line number Diff line
@@ -135,7 +135,8 @@ static void gfxhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 
	tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);

	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);

	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);



	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

			    ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);

	/* XXX for emulation, Refer to closed source code.*/

	tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL,

			    L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

+2 −0
Original line number Diff line number Diff line
@@ -121,6 +121,8 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev) 
	tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);

	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);

	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);

	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,

			    ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);

	/* XXX for emulation, Refer to closed source code.*/

	tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,

			    0);

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