Commit 3eaf3ca6 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'octeontx2-next' 

Jerin Jacob says:

====================
octeontx2-af: NIX and NPC enhancements

This patchset is a continuation to earlier submitted four patch
series to add a new driver for Marvell's OcteonTX2 SOC's
Resource virtualization unit (RVU) admin function driver.

1. octeontx2-af: Add RVU Admin Function driver
   https://www.spinics.net/lists/netdev/msg528272.html
2. octeontx2-af: NPA and NIX blocks initialization
   https://www.spinics.net/lists/netdev/msg529163.html
3. octeontx2-af: NPC parser and NIX blocks initialization
   https://www.spinics.net/lists/netdev/msg530252.html
4. octeontx2-af: NPC MCAM support and FLR handling
   https://www.spinics.net/lists/netdev/msg534392.html



This patch series adds support for below

NPC block:
- Add NPC(mkex) profile support for various Key extraction configurations

NIX block:
- Enable dynamic RSS flow key algorithm configuration
- Enhancements on Rx checksum and error checks
- Add support for Tx packet marking support
- TL1 schedule queue allocation enhancements
- Add LSO format configuration mbox
- VLAN TPID configuration
- Skip multicast entry init for broadcast tables

v2:

- Rename FLOW_* to NIX_FLOW_* to avoid serious global namespace collisions,
as we have various FLOW_* definitions coming from
include/uapi/linux/pkt_cls.h for example.(David Miller)
- Pack the arguments of rvu_get_tl1_schqs() function
as 80 columns allows.(David Miller)
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 6e360f73 23705adb

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

+54 −0
Original line number Diff line number Diff line
@@ -498,6 +498,60 @@ static inline bool cgx_event_is_linkevent(u64 event) 
		return false;

}



static inline int cgx_fwi_get_mkex_prfl_sz(u64 *prfl_sz,

					   struct cgx *cgx)

{

	u64 req = 0;

	u64 resp;

	int err;



	req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_MKEX_PRFL_SIZE, req);

	err = cgx_fwi_cmd_generic(req, &resp, cgx, 0);

	if (!err)

		*prfl_sz = FIELD_GET(RESP_MKEX_PRFL_SIZE, resp);



	return err;

}



static inline int cgx_fwi_get_mkex_prfl_addr(u64 *prfl_addr,

					     struct cgx *cgx)

{

	u64 req = 0;

	u64 resp;

	int err;



	req = FIELD_SET(CMDREG_ID, CGX_CMD_GET_MKEX_PRFL_ADDR, req);

	err = cgx_fwi_cmd_generic(req, &resp, cgx, 0);

	if (!err)

		*prfl_addr = FIELD_GET(RESP_MKEX_PRFL_ADDR, resp);



	return err;

}



int cgx_get_mkex_prfl_info(u64 *addr, u64 *size)

{

	struct cgx *cgx_dev;

	int err;



	if (!addr || !size)

		return -EINVAL;



	cgx_dev = list_first_entry(&cgx_list, struct cgx, cgx_list);

	if (!cgx_dev)

		return -ENXIO;



	err = cgx_fwi_get_mkex_prfl_sz(size, cgx_dev);

	if (err)

		return -EIO;



	err = cgx_fwi_get_mkex_prfl_addr(addr, cgx_dev);

	if (err)

		return -EIO;



	return 0;

}

EXPORT_SYMBOL(cgx_get_mkex_prfl_info);



static irqreturn_t cgx_fwi_event_handler(int irq, void *data)

{

	struct lmac *lmac = data;

drivers/net/ethernet/marvell/octeontx2/af/cgx.h

+1 −0
Original line number Diff line number Diff line
@@ -111,4 +111,5 @@ int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable); 
int cgx_get_link_info(void *cgxd, int lmac_id,

		      struct cgx_link_user_info *linfo);

int cgx_lmac_linkup_start(void *cgxd);

int cgx_get_mkex_prfl_info(u64 *addr, u64 *size);

#endif /* CGX_H */

drivers/net/ethernet/marvell/octeontx2/af/cgx_fw_if.h

+12 −0
Original line number Diff line number Diff line
@@ -78,6 +78,8 @@ enum cgx_cmd_id { 
	CGX_CMD_LINK_STATE_CHANGE,

	CGX_CMD_MODE_CHANGE,		/* hot plug support */

	CGX_CMD_INTF_SHUTDOWN,

	CGX_CMD_GET_MKEX_PRFL_SIZE,

	CGX_CMD_GET_MKEX_PRFL_ADDR

};



/* async event ids */
@@ -137,6 +139,16 @@ enum cgx_cmd_own { 
 */

#define RESP_MAC_ADDR		GENMASK_ULL(56, 9)



/* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_SIZE with cmd status as

 * CGX_STAT_SUCCESS

 */

#define RESP_MKEX_PRFL_SIZE		GENMASK_ULL(63, 9)



/* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_ADDR with cmd status as

 * CGX_STAT_SUCCESS

 */

#define RESP_MKEX_PRFL_ADDR		GENMASK_ULL(63, 9)



/* Response to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE

 * status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS

 *

drivers/net/ethernet/marvell/octeontx2/af/common.h

+3 −22
Original line number Diff line number Diff line
@@ -143,6 +143,9 @@ enum nix_scheduler { 
	NIX_TXSCH_LVL_CNT = 0x5,

};



#define TXSCH_TL1_DFLT_RR_QTM      ((1 << 24) - 1)

#define TXSCH_TL1_DFLT_RR_PRIO     (0x1ull)



/* Min/Max packet sizes, excluding FCS */

#define	NIC_HW_MIN_FRS			40

#define	NIC_HW_MAX_FRS			9212
@@ -193,26 +196,4 @@ enum nix_scheduler { 
#define DEFAULT_RSS_CONTEXT_GROUP	0

#define MAX_RSS_INDIR_TBL_SIZE		256 /* 1 << Max adder bits */



/* NIX flow tag, key type flags */

#define FLOW_KEY_TYPE_PORT	BIT(0)

#define FLOW_KEY_TYPE_IPV4	BIT(1)

#define FLOW_KEY_TYPE_IPV6	BIT(2)

#define FLOW_KEY_TYPE_TCP	BIT(3)

#define FLOW_KEY_TYPE_UDP	BIT(4)

#define FLOW_KEY_TYPE_SCTP	BIT(5)



/* NIX flow tag algorithm indices, max is 31 */

enum {

	FLOW_KEY_ALG_PORT,

	FLOW_KEY_ALG_IP,

	FLOW_KEY_ALG_TCP,

	FLOW_KEY_ALG_UDP,

	FLOW_KEY_ALG_SCTP,

	FLOW_KEY_ALG_TCP_UDP,

	FLOW_KEY_ALG_TCP_SCTP,

	FLOW_KEY_ALG_UDP_SCTP,

	FLOW_KEY_ALG_TCP_UDP_SCTP,

	FLOW_KEY_ALG_MAX,

};



#endif /* COMMON_H */

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+61 −1
Original line number Diff line number Diff line
@@ -193,12 +193,20 @@ M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, msg_rsp) \ 
M(NIX_STATS_RST,	0x8007, nix_stats_rst, msg_req, msg_rsp)	\

M(NIX_VTAG_CFG,		0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp)	\

M(NIX_RSS_FLOWKEY_CFG,  0x8009, nix_rss_flowkey_cfg,			\

				 nix_rss_flowkey_cfg, msg_rsp)		\

				 nix_rss_flowkey_cfg,			\

				 nix_rss_flowkey_cfg_rsp)		\

M(NIX_SET_MAC_ADDR,	0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \

M(NIX_SET_RX_MODE,	0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp)	\

M(NIX_SET_HW_FRS,	0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp)	\

M(NIX_LF_START_RX,	0x800d, nix_lf_start_rx, msg_req, msg_rsp)	\

M(NIX_LF_STOP_RX,	0x800e, nix_lf_stop_rx, msg_req, msg_rsp)	\

M(NIX_MARK_FORMAT_CFG,	0x800f, nix_mark_format_cfg,			\

				 nix_mark_format_cfg,			\

				 nix_mark_format_cfg_rsp)		\

M(NIX_SET_RX_CFG,	0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp)	\

M(NIX_LSO_FORMAT_CFG,	0x8011, nix_lso_format_cfg,			\

				 nix_lso_format_cfg,			\

				 nix_lso_format_cfg_rsp)		\

M(NIX_RXVLAN_ALLOC,	0x8012, nix_rxvlan_alloc, msg_req, msg_rsp)



/* Messages initiated by AF (range 0xC00 - 0xDFF) */
@@ -413,6 +421,10 @@ enum nix_af_status { 
	NIX_AF_INVAL_TXSCHQ_CFG     = -412,

	NIX_AF_SMQ_FLUSH_FAILED     = -413,

	NIX_AF_ERR_LF_RESET         = -414,

	NIX_AF_ERR_RSS_NOSPC_FIELD  = -415,

	NIX_AF_ERR_RSS_NOSPC_ALGO   = -416,

	NIX_AF_ERR_MARK_CFG_FAIL    = -417,

	NIX_AF_ERR_LSO_CFG_FAIL     = -418,

	NIX_AF_INVAL_NPA_PF_FUNC    = -419,

	NIX_AF_INVAL_SSO_PF_FUNC    = -420,

};
@@ -560,15 +572,40 @@ struct nix_vtag_config { 
struct nix_rss_flowkey_cfg {

	struct mbox_msghdr hdr;

	int	mcam_index;  /* MCAM entry index to modify */

#define NIX_FLOW_KEY_TYPE_PORT	BIT(0)

#define NIX_FLOW_KEY_TYPE_IPV4	BIT(1)

#define NIX_FLOW_KEY_TYPE_IPV6	BIT(2)

#define NIX_FLOW_KEY_TYPE_TCP	BIT(3)

#define NIX_FLOW_KEY_TYPE_UDP	BIT(4)

#define NIX_FLOW_KEY_TYPE_SCTP	BIT(5)

	u32	flowkey_cfg; /* Flowkey types selected */

	u8	group;       /* RSS context or group */

};



struct nix_rss_flowkey_cfg_rsp {

	struct mbox_msghdr hdr;

	u8	alg_idx; /* Selected algo index */

};



struct nix_set_mac_addr {

	struct mbox_msghdr hdr;

	u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */

};



struct nix_mark_format_cfg {

	struct mbox_msghdr hdr;

	u8 offset;

	u8 y_mask;

	u8 y_val;

	u8 r_mask;

	u8 r_val;

};



struct nix_mark_format_cfg_rsp {

	struct mbox_msghdr hdr;

	u8 mark_format_idx;

};



struct nix_rx_mode {

	struct mbox_msghdr hdr;

#define NIX_RX_MODE_UCAST	BIT(0)
@@ -577,6 +614,15 @@ struct nix_rx_mode { 
	u16	mode;

};



struct nix_rx_cfg {

	struct mbox_msghdr hdr;

#define NIX_RX_OL3_VERIFY   BIT(0)

#define NIX_RX_OL4_VERIFY   BIT(1)

	u8 len_verify; /* Outer L3/L4 len check */

#define NIX_RX_CSUM_OL4_VERIFY  BIT(0)

	u8 csum_verify; /* Outer L4 checksum verification */

};



struct nix_frs_cfg {

	struct mbox_msghdr hdr;

	u8	update_smq;    /* Update SMQ's min/max lens */
@@ -586,6 +632,18 @@ struct nix_frs_cfg { 
	u16	minlen;

};



struct nix_lso_format_cfg {

	struct mbox_msghdr hdr;

	u64 field_mask;

#define NIX_LSO_FIELD_MAX	8

	u64 fields[NIX_LSO_FIELD_MAX];

};



struct nix_lso_format_cfg_rsp {

	struct mbox_msghdr hdr;

	u8 lso_format_idx;

};



/* NPC mbox message structs */



#define NPC_MCAM_ENTRY_INVALID	0xFFFF
@@ -730,6 +788,8 @@ struct npc_get_kex_cfg_rsp { 
	u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];

	/* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */

	u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];

#define MKEX_NAME_LEN 128

	u8 mkex_pfl_name[MKEX_NAME_LEN];

};



#endif /* MBOX_H */

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