Commit 3ea59ace authored by Maxime Ripard's avatar Maxime Ripard Committed by Stephen Boyd
Browse files

clk: bcm: rpi: Split pllb clock hooks 



The driver only supports the pllb for now and all the clock framework hooks
are a mix of the generic firmware interface and the specifics of the pllb.
Since we will support more clocks in the future let's split the generic and
specific hooks

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: linux-clk@vger.kernel.org
Acked-by: default avatarNicolas Saenz Julienne <nsaenzjulienne@suse.de>
Reviewed-by: default avatarStephen Boyd <sboyd@kernel.org>
Tested-by: default avatarNicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/fdc21962fdc7de5c46232f198672d5d5c868ec74.1592210452.git-series.maxime@cerno.tech


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent c1ce3509

drivers/clk/bcm/clk-raspberrypi.c

+22 −8
Original line number Diff line number Diff line
@@ -102,7 +102,7 @@ static int raspberrypi_fw_is_prepared(struct clk_hw *hw) 
}





static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,

static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw,

					     unsigned long parent_rate)

{

	struct raspberrypi_clk_data *data =
@@ -116,21 +116,27 @@ static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw, 
	if (ret)

		return ret;



	return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;

	return val;

}



static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,

static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,

						 unsigned long parent_rate)

{

	return raspberrypi_fw_get_rate(hw, parent_rate) *

		RPI_FIRMWARE_PLLB_ARM_DIV_RATE;

}



static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,

				   unsigned long parent_rate)

{

	struct raspberrypi_clk_data *data =

		container_of(hw, struct raspberrypi_clk_data, hw);

	struct raspberrypi_clk *rpi = data->rpi;

	u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;

	u32 _rate = rate;

	int ret;



	ret = raspberrypi_clock_property(rpi->firmware, data,

					 RPI_FIRMWARE_SET_CLOCK_RATE,

					 &new_rate);

					 RPI_FIRMWARE_SET_CLOCK_RATE, &_rate);

	if (ret)

		dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d",

				    clk_hw_get_name(hw), ret);
@@ -138,6 +144,14 @@ static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
	return ret;

}



static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,

				       unsigned long parent_rate)

{

	u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;



	return raspberrypi_fw_set_rate(hw, new_rate, parent_rate);

}



/*

 * Sadly there is no firmware rate rounding interface. We borrowed it from

 * clk-bcm2835.

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