Commit 3e7abf81 authored by Andi Shyti's avatar Andi Shyti Committed by Chris Wilson
Browse files

drm/i915: Extract GT render power state management 



i915_irq.c is large. One reason for this is that has a large chunk of
the GT render power management stashed away in it. Extract that logic
out of i915_irq.c and intel_pm.c and put it under one roof.

Based on a patch by Chris Wilson.

Signed-off-by: default avatarAndi Shyti <andi.shyti@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191024211642.7688-1-chris@chris-wilson.co.uk
parent 35865aef

drivers/gpu/drm/i915/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -95,6 +95,7 @@ gt-y += \ 
	gt/intel_reset.o \

	gt/intel_ring.o \

	gt/intel_ring_submission.o \

	gt/intel_rps.o \

	gt/intel_sseu.o \

	gt/intel_timeline.o \

	gt/intel_workarounds.o

drivers/gpu/drm/i915/display/intel_display.c

+5 −3
Original line number Diff line number Diff line
@@ -55,6 +55,8 @@ 
#include "display/intel_tv.h"

#include "display/intel_vdsc.h"



#include "gt/intel_rps.h"



#include "i915_drv.h"

#include "i915_trace.h"

#include "intel_acpi.h"
@@ -14944,7 +14946,7 @@ static int do_rps_boost(struct wait_queue_entry *_wait, 
	 * vblank without our intervention, so leave RPS alone.

	 */

	if (!i915_request_started(rq))

		gen6_rps_boost(rq);

		intel_rps_boost(rq);

	i915_request_put(rq);



	drm_crtc_vblank_put(wait->crtc);
@@ -15138,7 +15140,7 @@ intel_prepare_plane_fb(struct drm_plane *plane, 
	 * maximum clocks following a vblank miss (see do_rps_boost()).

	 */

	if (!intel_state->rps_interactive) {

		intel_rps_mark_interactive(dev_priv, true);

		intel_rps_mark_interactive(&dev_priv->gt.rps, true);

		intel_state->rps_interactive = true;

	}
@@ -15163,7 +15165,7 @@ intel_cleanup_plane_fb(struct drm_plane *plane, 
	struct drm_i915_private *dev_priv = to_i915(plane->dev);



	if (intel_state->rps_interactive) {

		intel_rps_mark_interactive(dev_priv, false);

		intel_rps_mark_interactive(&dev_priv->gt.rps, false);

		intel_state->rps_interactive = false;

	}

drivers/gpu/drm/i915/gt/intel_gt.c

+3 −10
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ 
#include "intel_gt_requests.h"

#include "intel_mocs.h"

#include "intel_rc6.h"

#include "intel_rps.h"

#include "intel_uncore.h"

#include "intel_pm.h"
@@ -31,9 +32,6 @@ void intel_gt_init_early(struct intel_gt *gt, struct drm_i915_private *i915) 
void intel_gt_init_hw_early(struct drm_i915_private *i915)

{

	i915->gt.ggtt = &i915->ggtt;



	/* BIOS often leaves RC6 enabled, but disable it for hw init */

	intel_gt_pm_disable(&i915->gt);

}



static void init_unused_ring(struct intel_gt *gt, u32 base)
@@ -320,8 +318,7 @@ void intel_gt_chipset_flush(struct intel_gt *gt) 


void intel_gt_driver_register(struct intel_gt *gt)

{

	if (IS_GEN(gt->i915, 5))

		intel_gpu_ips_init(gt->i915);

	intel_rps_driver_register(&gt->rps);

}



static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
@@ -379,20 +376,16 @@ int intel_gt_init(struct intel_gt *gt) 
void intel_gt_driver_remove(struct intel_gt *gt)

{

	GEM_BUG_ON(gt->awake);

	intel_gt_pm_disable(gt);

}



void intel_gt_driver_unregister(struct intel_gt *gt)

{

	intel_gpu_ips_teardown();

	intel_rps_driver_unregister(&gt->rps);

}



void intel_gt_driver_release(struct intel_gt *gt)

{

	/* Paranoia: make sure we have disabled everything before we exit. */

	intel_gt_pm_disable(gt);

	intel_gt_pm_fini(gt);



	intel_gt_fini_scratch(gt);

}

drivers/gpu/drm/i915/gt/intel_gt_irq.c

+3 −2
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include "intel_gt.h"

#include "intel_gt_irq.h"

#include "intel_uncore.h"

#include "intel_rps.h"



static void guc_irq_handler(struct intel_guc *guc, u16 iir)

{
@@ -77,7 +78,7 @@ gen11_other_irq_handler(struct intel_gt *gt, const u8 instance, 
		return guc_irq_handler(&gt->uc.guc, iir);



	if (instance == OTHER_GTPM_INSTANCE)

		return gen11_rps_irq_handler(gt, iir);

		return gen11_rps_irq_handler(&gt->rps, iir);



	WARN_ONCE(1, "unhandled other interrupt instance=0x%x, iir=0x%x\n",

		  instance, iir);
@@ -336,7 +337,7 @@ void gen8_gt_irq_handler(struct intel_gt *gt, u32 master_ctl, u32 gt_iir[4]) 
	}



	if (master_ctl & (GEN8_GT_PM_IRQ | GEN8_GT_GUC_IRQ)) {

		gen6_rps_irq_handler(gt->i915, gt_iir[2]);

		gen6_rps_irq_handler(&gt->rps, gt_iir[2]);

		guc_irq_handler(&gt->uc.guc, gt_iir[2] >> 16);

	}

}

drivers/gpu/drm/i915/gt/intel_gt_pm.c

+13 −15
Original line number Diff line number Diff line
@@ -12,8 +12,10 @@ 
#include "intel_gt.h"

#include "intel_gt_pm.h"

#include "intel_gt_requests.h"

#include "intel_llc.h"

#include "intel_pm.h"

#include "intel_rc6.h"

#include "intel_rps.h"

#include "intel_wakeref.h"



static int __gt_unpark(struct intel_wakeref *wf)
@@ -39,12 +41,7 @@ static int __gt_unpark(struct intel_wakeref *wf) 
	gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);

	GEM_BUG_ON(!gt->awake);



	intel_enable_gt_powersave(i915);



	i915_update_gfx_val(i915);

	if (INTEL_GEN(i915) >= 6)

		gen6_rps_busy(i915);



	intel_rps_unpark(&gt->rps);

	i915_pmu_gt_unparked(i915);



	intel_gt_unpark_requests(gt);
@@ -64,8 +61,7 @@ static int __gt_park(struct intel_wakeref *wf) 


	i915_vma_parked(gt);

	i915_pmu_gt_parked(i915);

	if (INTEL_GEN(i915) >= 6)

		gen6_rps_idle(i915);

	intel_rps_park(&gt->rps);



	/* Everything switched off, flush any residual interrupt just in case */

	intel_synchronize_irq(i915);
@@ -97,6 +93,7 @@ void intel_gt_pm_init(struct intel_gt *gt) 
	 * user.

	 */

	intel_rc6_init(&gt->rc6);

	intel_rps_init(&gt->rps);

}



static bool reset_engines(struct intel_gt *gt)
@@ -140,12 +137,6 @@ void intel_gt_sanitize(struct intel_gt *gt, bool force) 
			engine->reset.finish(engine);

}



void intel_gt_pm_disable(struct intel_gt *gt)

{

	if (!is_mock_gt(gt))

		intel_sanitize_gt_powersave(gt->i915);

}



void intel_gt_pm_fini(struct intel_gt *gt)

{

	intel_rc6_fini(&gt->rc6);
@@ -164,9 +155,13 @@ int intel_gt_resume(struct intel_gt *gt) 
	 * allowing us to fixup the user contexts on their first pin.

	 */

	intel_gt_pm_get(gt);



	intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);

	intel_rc6_sanitize(&gt->rc6);



	intel_rps_enable(&gt->rps);

	intel_llc_enable(&gt->llc);



	for_each_engine(engine, gt, id) {

		struct intel_context *ce;
@@ -217,8 +212,11 @@ void intel_gt_suspend(struct intel_gt *gt) 
	/* We expect to be idle already; but also want to be independent */

	wait_for_idle(gt);



	with_intel_runtime_pm(gt->uncore->rpm, wakeref)

	with_intel_runtime_pm(gt->uncore->rpm, wakeref) {

		intel_rps_disable(&gt->rps);

		intel_rc6_disable(&gt->rc6);

		intel_llc_disable(&gt->llc);

	}

}



void intel_gt_runtime_suspend(struct intel_gt *gt)

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