Commit 3e4e1d3f authored by Christoph Hellwig's avatar Christoph Hellwig
Browse files

arm64: document the choice of page attributes for pgprot_dmacoherent 



Based on an email from Will Deacon.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Acked-by: default avatarWill Deacon <will@kernel.org>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
parent 8e3a68fb

arch/arm64/include/asm/pgtable.h

+8 −0
Original line number Original line Diff line number Diff line
@@ -435,6 +435,14 @@ static inline pmd_t pmd_mkdevmap(pmd_t pmd) 
	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)

	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)

#define pgprot_device(prot) \

#define pgprot_device(prot) \

	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)

	__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)

/*

 * DMA allocations for non-coherent devices use what the Arm architecture calls

 * "Normal non-cacheable" memory, which permits speculation, unaligned accesses

 * and merging of writes.  This is different from "Device-nGnR[nE]" memory which

 * is intended for MMIO and thus forbids speculation, preserves access size,

 * requires strict alignment and can also force write responses to come from the

 * endpoint.

 */

#define pgprot_dmacoherent(prot) \

#define pgprot_dmacoherent(prot) \

	__pgprot_modify(prot, PTE_ATTRINDX_MASK, \

	__pgprot_modify(prot, PTE_ATTRINDX_MASK, \

			PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)

			PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)

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