Commit 3e32131a authored by Zhang Lei's avatar Zhang Lei Committed by Catalin Marinas
Browse files

arm64: Add workaround for Fujitsu A64FX erratum 010001 



On the Fujitsu-A64FX cores ver(1.0, 1.1), memory access may cause
an undefined fault (Data abort, DFSC=0b111111). This fault occurs under
a specific hardware condition when a load/store instruction performs an
address translation. Any load/store instruction, except non-fault access
including Armv8 and SVE might cause this undefined fault.

The TCR_ELx.NFD1 bit is used by the kernel when CONFIG_RANDOMIZE_BASE
is enabled to mitigate timing attacks against KASLR where the kernel
address space could be probed using the FFR and suppressed fault on
SVE loads.

Since this erratum causes spurious exceptions, which may corrupt
the exception registers, we clear the TCR_ELx.NFDx=1 bits when
booting on an affected CPU.

Signed-off-by: default avatarZhang Lei <zhang.lei@jp.fujitsu.com>
[Generated MIDR value/mask for __cpu_setup(), removed spurious-fault handler
 and always disabled the NFDx bits on affected CPUs]
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Tested-by: default avatarzhang.lei <zhang.lei@jp.fujitsu.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 4caf8758

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -80,3 +80,4 @@ stable kernels. 
| Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |

| Qualcomm Tech. | QDF2400 ITS     | E0065           | QCOM_QDF2400_ERRATUM_0065   |

| Qualcomm Tech. | Falkor v{1,2}   | E1041           | QCOM_FALKOR_ERRATUM_1041    |

| Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |

arch/arm64/Kconfig

+19 −0
Original line number Diff line number Diff line
@@ -643,6 +643,25 @@ config QCOM_FALKOR_ERRATUM_E1041 


	  If unsure, say Y.



config FUJITSU_ERRATUM_010001

	bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"

	default y

	help

	  This option adds workaround for Fujitsu-A64FX erratum E#010001.

	  On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory

	  accesses may cause undefined fault (Data abort, DFSC=0b111111).

	  This fault occurs under a specific hardware condition when a

	  load/store instruction performs an address translation using:

	  case-1  TTBR0_EL1 with TCR_EL1.NFD0 == 1.

	  case-2  TTBR0_EL2 with TCR_EL2.NFD0 == 1.

	  case-3  TTBR1_EL1 with TCR_EL1.NFD1 == 1.

	  case-4  TTBR1_EL2 with TCR_EL2.NFD1 == 1.



	  The workaround is to ensure these bits are clear in TCR_ELx.

	  The workaround only affect the Fujitsu-A64FX.



	  If unsure, say Y.



endmenu

arch/arm64/include/asm/assembler.h

+20 −0
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ 


#include <asm/asm-offsets.h>

#include <asm/cpufeature.h>

#include <asm/cputype.h>

#include <asm/debug-monitors.h>

#include <asm/page.h>

#include <asm/pgtable-hwdef.h>
@@ -596,6 +597,25 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU 
#endif

	.endm



/*

 * tcr_clear_errata_bits - Clear TCR bits that trigger an errata on this CPU.

 */

	.macro	tcr_clear_errata_bits, tcr, tmp1, tmp2

#ifdef CONFIG_FUJITSU_ERRATUM_010001

	mrs	\tmp1, midr_el1



	mov_q	\tmp2, MIDR_FUJITSU_ERRATUM_010001_MASK

	and	\tmp1, \tmp1, \tmp2

	mov_q	\tmp2, MIDR_FUJITSU_ERRATUM_010001

	cmp	\tmp1, \tmp2

	b.ne	10f



	mov_q	\tmp2, TCR_CLEAR_FUJITSU_ERRATUM_010001

	bic	\tcr, \tcr, \tmp2

10:

#endif /* CONFIG_FUJITSU_ERRATUM_010001 */

	.endm



/**

 * Errata workaround prior to disable MMU. Insert an ISB immediately prior

 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.

arch/arm64/include/asm/cputype.h

+9 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ 
#define ARM_CPU_IMP_BRCM		0x42

#define ARM_CPU_IMP_QCOM		0x51

#define ARM_CPU_IMP_NVIDIA		0x4E

#define ARM_CPU_IMP_FUJITSU		0x46



#define ARM_CPU_PART_AEM_V8		0xD0F

#define ARM_CPU_PART_FOUNDATION		0xD00
@@ -104,6 +105,8 @@ 
#define NVIDIA_CPU_PART_DENVER		0x003

#define NVIDIA_CPU_PART_CARMEL		0x004



#define FUJITSU_CPU_PART_A64FX		0x001



#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -122,6 +125,12 @@ 
#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)

#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)

#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_FUJITSU_A64FX MIDR_CPU_MODEL(ARM_CPU_IMP_FUJITSU, FUJITSU_CPU_PART_A64FX)



/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX

#define MIDR_FUJITSU_ERRATUM_010001_MASK	(~MIDR_VARIANT(1))

#define TCR_CLEAR_FUJITSU_ERRATUM_010001	(TCR_NFD1 | TCR_NFD0)



#ifndef __ASSEMBLY__

arch/arm64/include/asm/pgtable-hwdef.h

+1 −0
Original line number Diff line number Diff line
@@ -302,6 +302,7 @@ 
#define TCR_TBI1		(UL(1) << 38)

#define TCR_HA			(UL(1) << 39)

#define TCR_HD			(UL(1) << 40)

#define TCR_NFD0		(UL(1) << 53)

#define TCR_NFD1		(UL(1) << 54)



/*

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