Commit 3d93f42d authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge branch 'clockevents/4.8' of... 

Merge branch 'clockevents/4.8' of http://git.linaro.org/people/daniel.lezcano/linux into timers/core

Pull the clockevents/clocksource tree from Daniel Lezcano:

  - Convert the clocksource-probe init functions to return a value in order to
    prepare the consolidation of the drivers using the DT. It is a big patchset
    but went through 01.org (kbuild bot), linux next and kernel-ci (continuous
    integration) (Daniel Lezcano)

  - Fix a bad error handling by returning the right value for cadence_ttc
    (Christophe Jaillet)

  - Fix typo in the Kconfig for the Samsung pwm (Alexandre Belloni)

  - Change functions to static for armada-370-xp and digicolor (Ben Dooks)

  - Add support for the rk3399 SoC timer by adding bindings and a slight
    change in the base address. Take the opportunity to add the DYNIRQ flag
    (Huang Tao)

  - Fix endian accessors for the Samsung pwm timer (Matthew Leach)

  - Add Oxford Semiconductor RPS Dual Timer driver (Neil Armstrong)

  - Add a kernel parameter to swich on/off the event stream feature of the arch
    arm timer (Will Deacon)
parents 4b4b2085 34c720a9

Documentation/devicetree/bindings/timer/oxsemi,rps-timer.txt

0 → 100644
+17 −0
Original line number Diff line number Diff line 
Oxford Semiconductor OXNAS SoCs Family RPS Timer

================================================



Required properties:

- compatible: Should be "oxsemi,ox810se-rps-timer"

- reg : Specifies base physical address and size of the registers.

- interrupts : The interrupts of the two timers

- clocks : The phandle of the timer clock source



example:



timer0: timer@200 {

	compatible = "oxsemi,ox810se-rps-timer";

	reg = <0x200 0x40>;

	clocks = <&rpsclk>;

	interrupts = <4 5>;

};

Documentation/devicetree/bindings/timer/rockchip,rk3288-timer.txt→Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt

+4 −2
Original line number Diff line number Diff line 
Rockchip rk3288 timer

Rockchip rk timer



Required properties:

- compatible: shall be "rockchip,rk3288-timer"

- compatible: shall be one of:

  "rockchip,rk3288-timer" - for rk3066, rk3036, rk3188, rk322x, rk3288, rk3368

  "rockchip,rk3399-timer" - for rk3399

- reg: base address of the timer register starting with TIMERS CONTROL register

- interrupts: should contain the interrupts for Timer0

- clocks : must contain an entry for each entry in clock-names

Documentation/kernel-parameters.txt

+8 −0
Original line number Diff line number Diff line
@@ -687,6 +687,14 @@ bytes respectively. Such letter suffixes can also be entirely omitted. 
			[SPARC64] tick

			[X86-64] hpet,tsc



	clocksource.arm_arch_timer.evtstrm=

			[ARM,ARM64]

			Format: <bool>

			Enable/disable the eventstream feature of the ARM

			architected timer so that code using WFE-based polling

			loops can be debugged more effectively on production

			systems.



	clearcpuid=BITNUM [X86]

			Disable CPUID feature X for the kernel. See

			arch/x86/include/asm/cpufeatures.h for the valid bit

arch/arc/kernel/time.c

+39 −24
Original line number Diff line number Diff line
@@ -116,19 +116,19 @@ static struct clocksource arc_counter_gfrc = { 
	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,

};



static void __init arc_cs_setup_gfrc(struct device_node *node)

static int __init arc_cs_setup_gfrc(struct device_node *node)

{

	int exists = cpuinfo_arc700[0].extn.gfrc;

	int ret;



	if (WARN(!exists, "Global-64-bit-Ctr clocksource not detected"))

		return;

		return -ENXIO;



	ret = arc_get_timer_clk(node);

	if (ret)

		return;

		return ret;



	clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);

	return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);

}

CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
@@ -172,25 +172,25 @@ static struct clocksource arc_counter_rtc = { 
	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,

};



static void __init arc_cs_setup_rtc(struct device_node *node)

static int __init arc_cs_setup_rtc(struct device_node *node)

{

	int exists = cpuinfo_arc700[smp_processor_id()].extn.rtc;

	int ret;



	if (WARN(!exists, "Local-64-bit-Ctr clocksource not detected"))

		return;

		return -ENXIO;



	/* Local to CPU hence not usable in SMP */

	if (WARN(IS_ENABLED(CONFIG_SMP), "Local-64-bit-Ctr not usable in SMP"))

		return;

		return -EINVAL;



	ret = arc_get_timer_clk(node);

	if (ret)

		return;

		return ret;



	write_aux_reg(AUX_RTC_CTRL, 1);



	clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);

	return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);

}

CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
@@ -213,23 +213,23 @@ static struct clocksource arc_counter_timer1 = { 
	.flags  = CLOCK_SOURCE_IS_CONTINUOUS,

};



static void __init arc_cs_setup_timer1(struct device_node *node)

static int __init arc_cs_setup_timer1(struct device_node *node)

{

	int ret;



	/* Local to CPU hence not usable in SMP */

	if (IS_ENABLED(CONFIG_SMP))

		return;

		return -EINVAL;



	ret = arc_get_timer_clk(node);

	if (ret)

		return;

		return ret;



	write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);

	write_aux_reg(ARC_REG_TIMER1_CNT, 0);

	write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);



	clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);

	return clocksource_register_hz(&arc_counter_timer1, arc_timer_freq);

}



/********** Clock Event Device *********/
@@ -324,20 +324,28 @@ static struct notifier_block arc_timer_cpu_nb = { 
/*

 * clockevent setup for boot CPU

 */

static void __init arc_clockevent_setup(struct device_node *node)

static int __init arc_clockevent_setup(struct device_node *node)

{

	struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);

	int ret;



	register_cpu_notifier(&arc_timer_cpu_nb);

	ret = register_cpu_notifier(&arc_timer_cpu_nb);

	if (ret) {

		pr_err("Failed to register cpu notifier");

		return ret;

	}



	arc_timer_irq = irq_of_parse_and_map(node, 0);

	if (arc_timer_irq <= 0)

		panic("clockevent: missing irq");

	if (arc_timer_irq <= 0) {

		pr_err("clockevent: missing irq");

		return -EINVAL;

	}



	ret = arc_get_timer_clk(node);

	if (ret)

		panic("clockevent: missing clk");

	if (ret) {

		pr_err("clockevent: missing clk");

		return ret;

	}



	evt->irq = arc_timer_irq;

	evt->cpumask = cpumask_of(smp_processor_id());
@@ -347,22 +355,29 @@ static void __init arc_clockevent_setup(struct device_node *node) 
	/* Needs apriori irq_set_percpu_devid() done in intc map function */

	ret = request_percpu_irq(arc_timer_irq, timer_irq_handler,

				 "Timer0 (per-cpu-tick)", evt);

	if (ret)

		panic("clockevent: unable to request irq\n");

	if (ret) {

		pr_err("clockevent: unable to request irq\n");

		return ret;

	}



	enable_percpu_irq(arc_timer_irq, 0);



	return 0;

}



static void __init arc_of_timer_init(struct device_node *np)

static int __init arc_of_timer_init(struct device_node *np)

{

	static int init_count = 0;

	int ret;



	if (!init_count) {

		init_count = 1;

		arc_clockevent_setup(np);

		ret = arc_clockevent_setup(np);

	} else {

		arc_cs_setup_timer1(np);

		ret = arc_cs_setup_timer1(np);

	}



	return ret;

}

CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);

arch/arm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -358,10 +358,10 @@ config ARCH_CLPS711X 
	bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"

	select ARCH_REQUIRE_GPIOLIB

	select AUTO_ZRELADDR

	select CLKSRC_MMIO

	select COMMON_CLK

	select CPU_ARM720T

	select GENERIC_CLOCKEVENTS

	select CLPS711X_TIMER

	select MFD_SYSCON

	select SOC_BUS

	help

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