Commit 3d8dfe75 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 updates from Catalin Marinas:

 - Pseudo NMI support for arm64 using GICv3 interrupt priorities

 - uaccess macros clean-up (unsafe user accessors also merged but
   reverted, waiting for objtool support on arm64)

 - ptrace regsets for Pointer Authentication (ARMv8.3) key management

 - inX() ordering w.r.t. delay() on arm64 and riscv (acks in place by
   the riscv maintainers)

 - arm64/perf updates: PMU bindings converted to json-schema, unused
   variable and misleading comment removed

 - arm64/debug fixes to ensure checking of the triggering exception
   level and to avoid the propagation of the UNKNOWN FAR value into the
   si_code for debug signals

 - Workaround for Fujitsu A64FX erratum 010001

 - lib/raid6 ARM NEON optimisations

 - NR_CPUS now defaults to 256 on arm64

 - Minor clean-ups (documentation/comments, Kconfig warning, unused
   asm-offsets, clang warnings)

 - MAINTAINERS update for list information to the ARM64 ACPI entry

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (54 commits)
  arm64: mmu: drop paging_init comments
  arm64: debug: Ensure debug handlers check triggering exception level
  arm64: debug: Don't propagate UNKNOWN FAR into si_code for debug signals
  Revert "arm64: uaccess: Implement unsafe accessors"
  arm64: avoid clang warning about self-assignment
  arm64: Kconfig.platforms: fix warning unmet direct dependencies
  lib/raid6: arm: optimize away a mask operation in NEON recovery routine
  lib/raid6: use vdupq_n_u8 to avoid endianness warnings
  arm64: io: Hook up __io_par() for inX() ordering
  riscv: io: Update __io_[p]ar() macros to take an argument
  asm-generic/io: Pass result of I/O accessor to __io_[p]ar()
  arm64: Add workaround for Fujitsu A64FX erratum 010001
  arm64: Rename get_thread_info()
  arm64: Remove documentation about TIF_USEDFPU
  arm64: irqflags: Fix clang build warnings
  arm64: Enable the support of pseudo-NMIs
  arm64: Skip irqflags tracing for NMI in IRQs disabled context
  arm64: Skip preemption when exiting an NMI
  arm64: Handle serror in NMI context
  irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI
  ...
parents d6075262 b855b58a

Documentation/admin-guide/kernel-parameters.txt

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Original line number Diff line number Diff line
@@ -1846,6 +1846,11 @@ 
			to let secondary kernels in charge of setting up

			LPIs.



	irqchip.gicv3_pseudo_nmi= [ARM64]

			Enables support for pseudo-NMIs in the kernel. This

			requires the kernel to be built with

			CONFIG_ARM64_PSEUDO_NMI.



	irqfixup	[HW]

			When an interrupt is not handled search all handlers

			for it. Intended to get systems with badly broken

Documentation/arm64/booting.txt

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@@ -188,6 +188,11 @@ Before jumping into the kernel, the following conditions must be met: 
  the kernel image will be entered must be initialised by software at a

  higher exception level to prevent execution in an UNKNOWN state.



  - SCR_EL3.FIQ must have the same value across all CPUs the kernel is

    executing on.

  - The value of SCR_EL3.FIQ must be the same as the one present at boot

    time whenever the kernel is executing.



  For systems with a GICv3 interrupt controller to be used in v3 mode:

  - If EL3 is present:

    ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.

Documentation/arm64/pointer-authentication.txt

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Original line number Diff line number Diff line
@@ -78,6 +78,11 @@ bits can vary between the two. Note that the masks apply to TTBR0 
addresses, and are not valid to apply to TTBR1 addresses (e.g. kernel

pointers).



Additionally, when CONFIG_CHECKPOINT_RESTORE is also set, the kernel

will expose the NT_ARM_PACA_KEYS and NT_ARM_PACG_KEYS regsets (struct

user_pac_address_keys and struct user_pac_generic_keys). These can be

used to get and set the keys for a thread.





Virtualization

--------------

Documentation/arm64/silicon-errata.txt

+1 −0
Original line number Diff line number Diff line
@@ -82,3 +82,4 @@ stable kernels. 
| Qualcomm Tech. | Falkor v1       | E1009           | QCOM_FALKOR_ERRATUM_1009    |

| Qualcomm Tech. | QDF2400 ITS     | E0065           | QCOM_QDF2400_ERRATUM_0065   |

| Qualcomm Tech. | Falkor v{1,2}   | E1041           | QCOM_FALKOR_ERRATUM_1041    |

| Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |

Documentation/devicetree/bindings/arm/pmu.txt

deleted100644 → 0
+0 −70
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* ARM Performance Monitor Units



ARM cores often have a PMU for counting cpu and cache events like cache misses

and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU

representation in the device tree should be done as under:-



Required properties:



- compatible : should be one of

	"apm,potenza-pmu"

	"arm,armv8-pmuv3"

	"arm,cortex-a73-pmu"

	"arm,cortex-a72-pmu"

	"arm,cortex-a57-pmu"

	"arm,cortex-a53-pmu"

	"arm,cortex-a35-pmu"

	"arm,cortex-a17-pmu"

	"arm,cortex-a15-pmu"

	"arm,cortex-a12-pmu"

	"arm,cortex-a9-pmu"

	"arm,cortex-a8-pmu"

	"arm,cortex-a7-pmu"

	"arm,cortex-a5-pmu"

	"arm,arm11mpcore-pmu"

	"arm,arm1176-pmu"

	"arm,arm1136-pmu"

	"brcm,vulcan-pmu"

	"cavium,thunder-pmu"

	"qcom,scorpion-pmu"

	"qcom,scorpion-mp-pmu"

	"qcom,krait-pmu"

- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu

               interrupt (PPI) then 1 interrupt should be specified.



Optional properties:



- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU

                       nodes corresponding directly to the affinity of

		       the SPIs listed in the interrupts property.



                       When using a PPI, specifies a list of phandles to CPU

		       nodes corresponding to the set of CPUs which have

		       a PMU of this type signalling the PPI listed in the

		       interrupts property, unless this is already specified

		       by the PPI interrupt specifier itself (in which case

		       the interrupt-affinity property shouldn't be present).



                       This property should be present when there is more than

		       a single SPI.





- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd

                     events.



- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register

		      (SDER) is accessible. This will cause the driver to do

		      any setup required that is only possible in ARMv7 secure

		      state. If not present the ARMv7 SDER will not be touched,

		      which means the PMU may fail to operate unless external

		      code (bootloader or security monitor) has performed the

		      appropriate initialisation. Note that this property is

		      not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux

		      in Non-secure state.



Example:



pmu {

        compatible = "arm,cortex-a9-pmu";

        interrupts = <100 101>;

};

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