Commit 3d5cc272 authored Feb 27, 2019 by Hugo Hu Committed by Alex Deucher Mar 20, 2019

drm/amd/display: Programming correct VRR_EN bit in VTEM structure



[Why]
In HDMI plugfest, MTK report our EMP with VRR_EN bit = 0.
VRR_EN bit is EMP-MD0-bit 0. Currently driver set 1 to bit 3.

[How]
Programming correct VRR_EN bit in EMP-MD0-bit0.

Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Reza Amini <Reza.Amini@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 8db89b2e

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -622,9 +622,9 @@ static void build_vrr_vtem_infopacket_data(const struct dc_stream_state *stream,

		if (vrr->state == VRR_STATE_ACTIVE_VARIABLE \|\|
		vrr->state == VRR_STATE_ACTIVE_FIXED){
		infopacket->sb[6] \|= 0x80; //VRR_EN Bit = 1
		infopacket->sb[6] \|= 0x01; //VRR_EN Bit = 1
		} else {
		infopacket->sb[6] &= 0x7F; //VRR_EN Bit = 0
		infopacket->sb[6] &= 0xFE; //VRR_EN Bit = 0
		}

		if (!stream->timing.vic) {

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