Commit 3d5ca1e6 authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Martin K. Petersen
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scsi: qla2xxx: use lower_32_bits and upper_32_bits instead of reinventing them



This also moves the optimization for builds with 32-bit dma_addr_t to
the compiler (where it belongs) instead of opencoding it based on
incorrect assumptions.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent ac4b1657
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+4 −4
Original line number Diff line number Diff line
@@ -2660,9 +2660,9 @@ static void qlt_load_cont_data_segments(struct qla_tgt_prm *prm)
		    cnt < QLA_TGT_DATASEGS_PER_CONT_24XX && prm->seg_cnt;
		    cnt++, prm->seg_cnt--) {
			*dword_ptr++ =
			    cpu_to_le32(pci_dma_lo32
			    cpu_to_le32(lower_32_bits
				(sg_dma_address(prm->sg)));
			*dword_ptr++ = cpu_to_le32(pci_dma_hi32
			*dword_ptr++ = cpu_to_le32(upper_32_bits
			    (sg_dma_address(prm->sg)));
			*dword_ptr++ = cpu_to_le32(sg_dma_len(prm->sg));

@@ -2704,9 +2704,9 @@ static void qlt_load_data_segments(struct qla_tgt_prm *prm)
	    (cnt < QLA_TGT_DATASEGS_PER_CMD_24XX) && prm->seg_cnt;
	    cnt++, prm->seg_cnt--) {
		*dword_ptr++ =
		    cpu_to_le32(pci_dma_lo32(sg_dma_address(prm->sg)));
		    cpu_to_le32(lower_32_bits(sg_dma_address(prm->sg)));

		*dword_ptr++ = cpu_to_le32(pci_dma_hi32(
		*dword_ptr++ = cpu_to_le32(upper_32_bits(
			sg_dma_address(prm->sg)));

		*dword_ptr++ = cpu_to_le32(sg_dma_len(prm->sg));
+0 −8
Original line number Diff line number Diff line
@@ -771,14 +771,6 @@ int qla2x00_wait_for_hba_online(struct scsi_qla_host *);
#define	FC_TM_REJECT                4
#define FC_TM_FAILED                5

#if (BITS_PER_LONG > 32) || defined(CONFIG_HIGHMEM64G)
#define pci_dma_lo32(a) (a & 0xffffffff)
#define pci_dma_hi32(a) ((((a) >> 16)>>16) & 0xffffffff)
#else
#define pci_dma_lo32(a) (a & 0xffffffff)
#define pci_dma_hi32(a) 0
#endif

#define QLA_TGT_SENSE_VALID(sense)  ((sense != NULL) && \
				(((const uint8_t *)(sense))[0] & 0x70) == 0x70)