Commit 3d5c5207 authored by Emil Tantilov's avatar Emil Tantilov Committed by Jeff Kirsher
Browse files

ixgbe: move disabling of relaxed ordering in start_hw() 



Relaxed ordering can lead to issues with some chipsets.

This patch makes sure that it is disabled by default and
not only when DCA is on.

Signed-off-by: default avatarEmil Tantilov <emil.s.tantilov@intel.com>
Tested-by: default avatarEvan Swanson <evan.swanson@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 7184b7cf

drivers/net/ixgbe/ixgbe_82598.c

+20 −1
Original line number Diff line number Diff line
@@ -197,14 +197,33 @@ out: 
 *  @hw: pointer to hardware structure

 *

 *  Starts the hardware using the generic start_hw function.

 *  Then set pcie completion timeout

 *  Disables relaxed ordering Then set pcie completion timeout

 *

 **/

static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)

{

	u32 regval;

	u32 i;

	s32 ret_val = 0;



	ret_val = ixgbe_start_hw_generic(hw);



	/* Disable relaxed ordering */

	for (i = 0; ((i < hw->mac.max_tx_queues) &&

	     (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {

		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));

		regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;

		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);

	}



	for (i = 0; ((i < hw->mac.max_rx_queues) &&

	     (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {

		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));

		regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |

			    IXGBE_DCA_RXCTRL_DESC_HSRO_EN);

		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);

	}



	/* set the completion timeout for interface */

	if (ret_val == 0)

		ixgbe_set_pcie_completion_timeout(hw);

drivers/net/ixgbe/ixgbe_common.c

+15 −0
Original line number Diff line number Diff line
@@ -108,6 +108,7 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 
s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)

{

	u32 i;

	u32 regval;



	/* Clear the rate limiters */

	for (i = 0; i < hw->mac.max_tx_queues; i++) {
@@ -116,6 +117,20 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 
	}

	IXGBE_WRITE_FLUSH(hw);



	/* Disable relaxed ordering */

	for (i = 0; i < hw->mac.max_tx_queues; i++) {

		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));

		regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;

		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);

	}



	for (i = 0; i < hw->mac.max_rx_queues; i++) {

		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));

		regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |

					IXGBE_DCA_RXCTRL_DESC_HSRO_EN);

		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);

	}



	return 0;

}

drivers/net/ixgbe/ixgbe_main.c

+0 −4
Original line number Diff line number Diff line
@@ -947,8 +947,6 @@ static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, 
	rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;

	rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;

	rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);

	rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |

		    IXGBE_DCA_RXCTRL_DESC_HSRO_EN);

	IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);

}
@@ -966,7 +964,6 @@ static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 
		txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;

		txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);

		txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;

		txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;

		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);

		break;

	case ixgbe_mac_82599EB:
@@ -976,7 +973,6 @@ static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, 
		txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<

			   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);

		txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;

		txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;

		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);

		break;

	default:

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