Commit 3d581b11 authored by Frederick Lawler's avatar Frederick Lawler Committed by Bjorn Helgaas
Browse files

drm/radeon: Prefer pcie_capability_read_word() 

Commit 8c0d3a02 ("PCI: Add accessors for PCI Express Capability")
added accessors for the PCI Express Capability so that drivers didn't
need to be aware of differences between v1 and v2 of the PCI
Express Capability.

Replace pci_read_config_word() and pci_write_config_word() calls with
pcie_capability_read_word() and pcie_capability_write_word().

Link: https://lore.kernel.org/r/20191118003513.10852-1-fred@fredlawl.com


Signed-off-by: default avatarFrederick Lawler <fred@fredlawl.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ca56f99c

drivers/gpu/drm/radeon/cik.c

+44 −26
Original line number Diff line number Diff line
@@ -9504,7 +9504,6 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) 
{

	struct pci_dev *root = rdev->pdev->bus->self;

	enum pci_bus_speed speed_cap;

	int bridge_pos, gpu_pos;

	u32 speed_cntl, current_data_rate;

	int i;

	u16 tmp16;
@@ -9546,12 +9545,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) 
		DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");

	}



	bridge_pos = pci_pcie_cap(root);

	if (!bridge_pos)

		return;



	gpu_pos = pci_pcie_cap(rdev->pdev);

	if (!gpu_pos)

	if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))

		return;



	if (speed_cap == PCIE_SPEED_8_0GT) {
@@ -9561,14 +9555,17 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) 
			u16 bridge_cfg2, gpu_cfg2;

			u32 max_lw, current_lw, tmp;



			pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);

			pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);

			pcie_capability_read_word(root, PCI_EXP_LNKCTL,

						  &bridge_cfg);

			pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,

						  &gpu_cfg);



			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;

			pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);

			pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);



			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;

			pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);

			pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,

						   tmp16);



			tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);

			max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@@ -9586,15 +9583,23 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) 


			for (i = 0; i < 10; i++) {

				/* check status */

				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);

				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_DEVSTA,

							  &tmp16);

				if (tmp16 & PCI_EXP_DEVSTA_TRPND)

					break;



				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);

				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &bridge_cfg);

				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_LNKCTL,

							  &gpu_cfg);



				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);

				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

							  &bridge_cfg2);

				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_LNKCTL2,

							  &gpu_cfg2);



				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);

				tmp |= LC_SET_QUIESCE;
@@ -9607,32 +9612,45 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) 
				msleep(100);



				/* linkctl */

				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);

				pcie_capability_write_word(root, PCI_EXP_LNKCTL,

							   tmp16);



				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);

				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);

				pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);

				pcie_capability_write_word(rdev->pdev,

							   PCI_EXP_LNKCTL,

							   tmp16);



				/* linkctl2 */

				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (bridge_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);

				pcie_capability_write_word(root,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (gpu_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);

				pcie_capability_write_word(rdev->pdev,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);

				tmp &= ~LC_SET_QUIESCE;
@@ -9646,7 +9664,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) 
	speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;

	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);



	pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

	pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;

	if (speed_cap == PCIE_SPEED_8_0GT)

		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
@@ -9654,7 +9672,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) 
		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */

	else

		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */

	pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);

	pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);



	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

	speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;

drivers/gpu/drm/radeon/si.c

+46 −27
Original line number Diff line number Diff line
@@ -7087,7 +7087,6 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 
{

	struct pci_dev *root = rdev->pdev->bus->self;

	enum pci_bus_speed speed_cap;

	int bridge_pos, gpu_pos;

	u32 speed_cntl, current_data_rate;

	int i;

	u16 tmp16;
@@ -7129,12 +7128,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 
		DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");

	}



	bridge_pos = pci_pcie_cap(root);

	if (!bridge_pos)

		return;



	gpu_pos = pci_pcie_cap(rdev->pdev);

	if (!gpu_pos)

	if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev))

		return;



	if (speed_cap == PCIE_SPEED_8_0GT) {
@@ -7144,14 +7138,17 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 
			u16 bridge_cfg2, gpu_cfg2;

			u32 max_lw, current_lw, tmp;



			pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);

			pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);

			pcie_capability_read_word(root, PCI_EXP_LNKCTL,

						  &bridge_cfg);

			pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL,

						  &gpu_cfg);



			tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;

			pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);

			pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16);



			tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;

			pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);

			pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL,

						   tmp16);



			tmp = RREG32_PCIE(PCIE_LC_STATUS1);

			max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
@@ -7169,15 +7166,23 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 


			for (i = 0; i < 10; i++) {

				/* check status */

				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);

				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_DEVSTA,

							  &tmp16);

				if (tmp16 & PCI_EXP_DEVSTA_TRPND)

					break;



				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);

				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &bridge_cfg);

				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_LNKCTL,

							  &gpu_cfg);



				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);

				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

							  &bridge_cfg2);

				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_LNKCTL2,

							  &gpu_cfg2);



				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);

				tmp |= LC_SET_QUIESCE;
@@ -7190,32 +7195,46 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 
				msleep(100);



				/* linkctl */

				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);

				pcie_capability_write_word(root,

							   PCI_EXP_LNKCTL,

							   tmp16);



				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);

				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_LNKCTL,

							  &tmp16);

				tmp16 &= ~PCI_EXP_LNKCTL_HAWD;

				tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);

				pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);

				pcie_capability_write_word(rdev->pdev,

							   PCI_EXP_LNKCTL,

							   tmp16);



				/* linkctl2 */

				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);

				pcie_capability_read_word(root, PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (bridge_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);

				pcie_capability_write_word(root,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

				pcie_capability_read_word(rdev->pdev,

							  PCI_EXP_LNKCTL2,

							  &tmp16);

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (gpu_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);

				pcie_capability_write_word(rdev->pdev,

							   PCI_EXP_LNKCTL2,

							   tmp16);



				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);

				tmp &= ~LC_SET_QUIESCE;
@@ -7229,7 +7248,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 
	speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;

	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);



	pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

	pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;

	if (speed_cap == PCIE_SPEED_8_0GT)

		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
@@ -7237,7 +7256,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) 
		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */

	else

		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */

	pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);

	pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16);



	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);

	speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;

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