Commit 3d5128c1 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'irqchip-5.9' of... 

Merge tag 'irqchip-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

Pull irqchip updates from Marc Zyngier:

 - Add infrastructure to allow DT irqchip platform drivers to
   be built as modules
 - Allow qcom-pdc, mtk-cirq and mtk-sysirq to be built as module
 - Fix ACPI probing to avoid abusing function pointer casting
 - Allow bcm7120-l2 and brcmstb-l2 to be used as wake-up sources
 - Teach NXP's IMX INTMUX some power management
 - Allow stm32-exti to be used as a hierarchical irqchip
 - Let stm32-exti use the hw spinlock API in its full glory
 - A couple of GICv4.1 fixes
 - Tons of cleanups (mtk-sysirq, aic5, bcm7038-l1, imx-intmux,
   brcmstb-l2, ativic32, ti-sci-inta, lonsoon, MIPS GIC, GICv3)
parents 8fa88a88 ac62460c

Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt

+4 −1
Original line number Diff line number Diff line
@@ -2,7 +2,10 @@ Broadcom Generic Level 2 Interrupt Controller 


Required properties:



- compatible: should be "brcm,l2-intc" for latched interrupt controllers

- compatible: should be one of:

	      "brcm,hif-spi-l2-intc" or

	      "brcm,upg-aux-aon-l2-intc" or

	      "brcm,l2-intc" for latched interrupt controllers

              should be "brcm,bcm7271-l2-intc" for level interrupt controllers

- reg: specifies the base physical address and size of the registers

- interrupt-controller: identifies the node as an interrupt controller

Documentation/devicetree/bindings/interrupt-controller/loongson,htvec.yaml

+2 −2
Original line number Diff line number Diff line
@@ -22,8 +22,8 @@ properties: 


  interrupts:

    minItems: 1

    maxItems: 4

    description: Four parent interrupts that receive chained interrupts.

    maxItems: 8

    description: Eight parent interrupts that receive chained interrupts.



  interrupt-controller: true

drivers/irqchip/Kconfig

+1 −2
Original line number Diff line number Diff line
@@ -425,7 +425,7 @@ config GOLDFISH_PIC 
         for Goldfish based virtual platforms.



config QCOM_PDC

	bool "QCOM PDC"

	tristate "QCOM PDC"

	depends on ARCH_QCOM

	select IRQ_DOMAIN_HIERARCHY

	help
@@ -541,7 +541,6 @@ config LOONGSON_HTPIC 
	default y

	select IRQ_DOMAIN

	select GENERIC_IRQ_CHIP

	select I8259

	help

	  Support for the Loongson-3 HyperTransport PIC Controller.

drivers/irqchip/irq-ativic32.c

+1 −1
Original line number Diff line number Diff line
@@ -92,7 +92,7 @@ static int ativic32_irq_domain_map(struct irq_domain *id, unsigned int virq, 
	return 0;

}



static struct irq_domain_ops ativic32_ops = {

static const struct irq_domain_ops ativic32_ops = {

	.map = ativic32_irq_domain_map,

	.xlate = irq_domain_xlate_onecell

};

drivers/irqchip/irq-atmel-aic5.c

+7 −1
Original line number Diff line number Diff line
@@ -310,10 +310,16 @@ static void __init sama5d3_aic_irq_fixup(void) 
	aic_common_rtc_irq_fixup();

}



static void __init sam9x60_aic_irq_fixup(void)

{

	aic_common_rtc_irq_fixup();

	aic_common_rtt_irq_fixup();

}



static const struct of_device_id aic5_irq_fixups[] __initconst = {

	{ .compatible = "atmel,sama5d3", .data = sama5d3_aic_irq_fixup },

	{ .compatible = "atmel,sama5d4", .data = sama5d3_aic_irq_fixup },

	{ .compatible = "microchip,sam9x60", .data = sama5d3_aic_irq_fixup },

	{ .compatible = "microchip,sam9x60", .data = sam9x60_aic_irq_fixup },

	{ /* sentinel */ },

};

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