drm/mediatek: add the mipitx driving control (3d50b59a) · Commits · 戴 / test

drivers/gpu/drm/mediatek/mtk_mipi_tx.c

+14 −0

Original line number	Diff line number	Diff line
		@@ -125,6 +125,20 @@ static int mtk_mipi_tx_probe(struct platform_device *pdev)
		return ret;
		}

		ret = of_property_read_u32(dev->of_node, "drive-strength-microamp",
		&mipi_tx->mipitx_drive);
		/* If can't get the "mipi_tx->mipitx_drive", set it default 0x8 */
		if (ret < 0)
		mipi_tx->mipitx_drive = 4600;

		/* check the mipitx_drive valid */
		if (mipi_tx->mipitx_drive > 6000 \|\| mipi_tx->mipitx_drive < 3000) {
		dev_warn(dev, "drive-strength-microamp is invalid %d, not in 3000 ~ 6000\n",
		mipi_tx->mipitx_drive);
		mipi_tx->mipitx_drive = clamp_val(mipi_tx->mipitx_drive, 3000,
		6000);
		}

		ref_clk_name = __clk_get_name(ref_clk);

		ret = of_property_read_string(dev->of_node, "clock-output-names",

+1 −0

Original line number	Diff line number	Diff line
		@@ -27,6 +27,7 @@ struct mtk_mipi_tx {
		struct device *dev;
		void __iomem *regs;
		u32 data_rate;
		u32 mipitx_drive;
		const struct mtk_mipitx_data *driver_data;
		struct clk_hw pll_hw;
		struct clk *pll;

+7 −0

Original line number	Diff line number	Diff line
		@@ -17,6 +17,9 @@
		#define RG_DSI_BG_CORE_EN BIT(7)
		#define RG_DSI_PAD_TIEL_SEL BIT(8)

		#define MIPITX_VOLTAGE_SEL 0x0010
		#define RG_DSI_HSTX_LDO_REF_SEL (0xf << 6)

		#define MIPITX_PLL_PWR 0x0028
		#define MIPITX_PLL_CON0 0x002c
		#define MIPITX_PLL_CON1 0x0030
		@@ -123,6 +126,10 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy)
		mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
		mtk_mipi_tx_clear_bits(mipi_tx, MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);

		mtk_mipi_tx_update_bits(mipi_tx, MIPITX_VOLTAGE_SEL,
		RG_DSI_HSTX_LDO_REF_SEL,
		(mipi_tx->mipitx_drive - 3000) / 200 << 6);

		mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
		}