Commit 3d47fd47 authored by Stephane Viau's avatar Stephane Viau Committed by Rob Clark
Browse files

drm/msm/mdp5: add support for MDP5 v1.3 



MDP5 has several functional blocks (ie: VIG/RGB pipes, LMs, ...).
From one revision to another, these blocks' base addresses might
change due to the number of instances present in the MDP5 hw.
A way of dealing with these offset changes is to introduce
dynamic offsets 'per block'.

This change adds support for the new revision of MDP5: v1.3.
The idea is to define one hw config per MDP version and select
either one of them at runtime, after reading the MDP5 version.

Once the MDP version is known, 'per block' dynamic offsets
are initialized through a global pointer, which is then used for
read/write register access.

Signed-off-by: default avatarStephane Viau <sviau@codeaurora.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent a1ad3523

drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h

+264 −161

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c

+132 −19
Original line number Diff line number Diff line
@@ -26,14 +26,98 @@ static const char *iommu_ports[] = { 


static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev);



static int mdp5_hw_init(struct msm_kms *kms)

const struct mdp5_config *mdp5_cfg;



static const struct mdp5_config msm8x74_config = {

	.name = "msm8x74",

	.ctl = {

		.count = 5,

		.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },

	},

	.pipe_vig = {

		.count = 3,

		.base = { 0x01200, 0x01600, 0x01a00 },

	},

	.pipe_rgb = {

		.count = 3,

		.base = { 0x01e00, 0x02200, 0x02600 },

	},

	.pipe_dma = {

		.count = 2,

		.base = { 0x02a00, 0x02e00 },

	},

	.lm = {

		.count = 5,

		.base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 },

	},

	.dspp = {

		.count = 3,

		.base = { 0x04600, 0x04a00, 0x04e00 },

	},

	.ad = {

		.count = 2,

		.base = { 0x13100, 0x13300 }, /* NOTE: no ad in v1.0 */

	},

	.intf = {

		.count = 4,

		.base = { 0x12500, 0x12700, 0x12900, 0x12b00 },

	},

};



static const struct mdp5_config apq8084_config = {

	.name = "apq8084",

	.ctl = {

		.count = 5,

		.base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 },

	},

	.pipe_vig = {

		.count = 4,

		.base = { 0x01200, 0x01600, 0x01a00, 0x01e00 },

	},

	.pipe_rgb = {

		.count = 4,

		.base = { 0x02200, 0x02600, 0x02a00, 0x02e00 },

	},

	.pipe_dma = {

		.count = 2,

		.base = { 0x03200, 0x03600 },

	},

	.lm = {

		.count = 6,

		.base = { 0x03a00, 0x03e00, 0x04200, 0x04600, 0x04a00, 0x04e00 },

	},

	.dspp = {

		.count = 4,

		.base = { 0x05200, 0x05600, 0x05a00, 0x05e00 },



	},

	.ad = {

		.count = 3,

		.base = { 0x13500, 0x13700, 0x13900 },

	},

	.intf = {

		.count = 5,

		.base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 },

	},

};



struct mdp5_config_entry {

	int revision;

	const struct mdp5_config *config;

};



static const struct mdp5_config_entry mdp5_configs[] = {

	{ .revision = 0, .config = &msm8x74_config },

	{ .revision = 2, .config = &msm8x74_config },

	{ .revision = 3, .config = &apq8084_config },

};



static int mdp5_select_hw_cfg(struct msm_kms *kms)

{

	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

	struct drm_device *dev = mdp5_kms->dev;

	uint32_t version, major, minor;

	int ret = 0;



	pm_runtime_get_sync(dev->dev);

	int i, ret = 0;



	mdp5_enable(mdp5_kms);

	version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION);
@@ -44,8 +128,8 @@ static int mdp5_hw_init(struct msm_kms *kms) 


	DBG("found MDP5 version v%d.%d", major, minor);



	if ((major != 1) || ((minor != 0) && (minor != 2))) {

		dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",

	if (major != 1) {

		dev_err(dev->dev, "unexpected MDP major version: v%d.%d\n",

				major, minor);

		ret = -ENXIO;

		goto out;
@@ -53,6 +137,35 @@ static int mdp5_hw_init(struct msm_kms *kms) 


	mdp5_kms->rev = minor;



	/* only after mdp5_cfg global pointer's init can we access the hw */

	for (i = 0; i < ARRAY_SIZE(mdp5_configs); i++) {

		if (mdp5_configs[i].revision != minor)

			continue;

		mdp5_kms->hw_cfg = mdp5_cfg = mdp5_configs[i].config;

		break;

	}

	if (unlikely(!mdp5_kms->hw_cfg)) {

		dev_err(dev->dev, "unexpected MDP minor revision: v%d.%d\n",

				major, minor);

		ret = -ENXIO;

		goto out;

	}



	DBG("MDP5: %s config selected", mdp5_kms->hw_cfg->name);



	return 0;

out:

	return ret;

}



static int mdp5_hw_init(struct msm_kms *kms)

{

	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));

	struct drm_device *dev = mdp5_kms->dev;

	int i;



	pm_runtime_get_sync(dev->dev);



	/* Magic unknown register writes:

	 *

	 *    W VBIF:0x004 00000001      (mdss_mdp.c:839)
@@ -78,15 +191,13 @@ static int mdp5_hw_init(struct msm_kms *kms) 
	 */



	mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);

	mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(0), 0);

	mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(1), 0);

	mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(2), 0);

	mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(3), 0);



out:

	for (i = 0; i < mdp5_kms->hw_cfg->ctl.count; i++)

		mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(i), 0);



	pm_runtime_put_sync(dev->dev);



	return ret;

	return 0;

}



static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
@@ -161,7 +272,7 @@ int mdp5_enable(struct mdp5_kms *mdp5_kms) 
static int modeset_init(struct mdp5_kms *mdp5_kms)

{

	static const enum mdp5_pipe crtcs[] = {

			SSPP_RGB0, SSPP_RGB1, SSPP_RGB2,

			SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,

	};

	struct drm_device *dev = mdp5_kms->dev;

	struct msm_drm_private *priv = dev->dev_private;
@@ -169,7 +280,7 @@ static int modeset_init(struct mdp5_kms *mdp5_kms) 
	int i, ret;



	/* construct CRTCs: */

	for (i = 0; i < ARRAY_SIZE(crtcs); i++) {

	for (i = 0; i < mdp5_kms->hw_cfg->pipe_rgb.count; i++) {

		struct drm_plane *plane;

		struct drm_crtc *crtc;
@@ -246,7 +357,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) 
	struct mdp5_kms *mdp5_kms;

	struct msm_kms *kms = NULL;

	struct msm_mmu *mmu;

	int ret;

	int i, ret;



	mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);

	if (!mdp5_kms) {
@@ -307,15 +418,17 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) 


	ret = clk_set_rate(mdp5_kms->src_clk, config->max_clk);



	ret = mdp5_select_hw_cfg(kms);

	if (ret)

		goto fail;



	/* make sure things are off before attaching iommu (bootloader could

	 * have left things on, in which case we'll start getting faults if

	 * we don't disable):

	 */

	mdp5_enable(mdp5_kms);

	mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(0), 0);

	mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(1), 0);

	mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(2), 0);

	mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(3), 0);

	for (i = 0; i < mdp5_kms->hw_cfg->intf.count; i++)

		mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);

	mdp5_disable(mdp5_kms);

	mdelay(16);

drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h

+25 −0
Original line number Diff line number Diff line
@@ -21,6 +21,24 @@ 
#include "msm_drv.h"

#include "msm_kms.h"

#include "mdp/mdp_kms.h"

/* dynamic offsets used by mdp5.xml.h (initialized in mdp5_kms.c) */

#define MDP5_MAX_BASES		8

struct mdp5_sub_block {

	int	count;

	uint32_t base[MDP5_MAX_BASES];

};

struct mdp5_config {

	char  *name;

	struct mdp5_sub_block ctl;

	struct mdp5_sub_block pipe_vig;

	struct mdp5_sub_block pipe_rgb;

	struct mdp5_sub_block pipe_dma;

	struct mdp5_sub_block lm;

	struct mdp5_sub_block dspp;

	struct mdp5_sub_block ad;

	struct mdp5_sub_block intf;

};

extern const struct mdp5_config *mdp5_cfg;

#include "mdp5.xml.h"

#include "mdp5_smp.h"
@@ -30,6 +48,7 @@ struct mdp5_kms { 
	struct drm_device *dev;



	int rev;

	const struct mdp5_config *hw_cfg;



	/* mapper-id used to request GEM buffer mapped for scanout: */

	int id;
@@ -82,6 +101,7 @@ static inline const char *pipe2name(enum mdp5_pipe pipe) 
		NAME(VIG0), NAME(VIG1), NAME(VIG2),

		NAME(RGB0), NAME(RGB1), NAME(RGB2),

		NAME(DMA0), NAME(DMA1),

		NAME(VIG3), NAME(RGB3),

#undef NAME

	};

	return names[pipe];
@@ -98,6 +118,8 @@ static inline uint32_t pipe2flush(enum mdp5_pipe pipe) 
	case SSPP_RGB2: return MDP5_CTL_FLUSH_RGB2;

	case SSPP_DMA0: return MDP5_CTL_FLUSH_DMA0;

	case SSPP_DMA1: return MDP5_CTL_FLUSH_DMA1;

	case SSPP_VIG3: return MDP5_CTL_FLUSH_VIG3;

	case SSPP_RGB3: return MDP5_CTL_FLUSH_RGB3;

	default:        return 0;

	}

}
@@ -108,6 +130,7 @@ static inline int pipe2nclients(enum mdp5_pipe pipe) 
	case SSPP_RGB0:

	case SSPP_RGB1:

	case SSPP_RGB2:

	case SSPP_RGB3:

		return 1;

	default:

		return 3;
@@ -126,6 +149,8 @@ static inline enum mdp5_client_id pipe2client(enum mdp5_pipe pipe, int plane) 
	case SSPP_RGB2: return CID_RGB2;

	case SSPP_DMA0: return CID_DMA0_Y + plane;

	case SSPP_DMA1: return CID_DMA1_Y + plane;

	case SSPP_VIG3: return CID_VIG3_Y + plane;

	case SSPP_RGB3: return CID_RGB3;

	default:        return CID_UNUSED;

	}

}

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