Commit 3d372548 authored by James.Yang's avatar James.Yang Committed by Paul Mackerras
Browse files

[POWERPC] Remove CPU_FTR_NEED_COHERENT for 7448. 



Remove CPU_FTR_NEED_COHERENT for MPC7448 (and single-core MPC86xx).
This prevents needlessly setting M=1 when not SMP.

Signed-off-by: default avatarJames.Yang <James.Yang@freescale.com>
Acked-by: default avatarJon Loeliger <jdl@freescale.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent f4dcd3c2

arch/powerpc/kernel/cputable.c

+1 −1
Original line number Diff line number Diff line
@@ -836,7 +836,7 @@ static struct cpu_spec cpu_specs[] = { 
		.pvr_mask		= 0xffff0000,

		.pvr_value		= 0x80040000,

		.cpu_name		= "7448",

		.cpu_features		= CPU_FTRS_7447A,

		.cpu_features		= CPU_FTRS_7448,

		.cpu_user_features	= COMMON_USER |

			PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE,

		.icache_bsize		= 32,

include/asm-powerpc/cputable.h

+6 −0
Original line number Diff line number Diff line
@@ -302,6 +302,12 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start, 
	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)

#define CPU_FTRS_7448	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \

	    CPU_FTR_USE_TB | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \

	    CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \

	    CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \

	    CPU_FTR_PPC_LE)

#define CPU_FTRS_82XX	(CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \

	    CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)

#define CPU_FTRS_G2_LE	(CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \

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