cxl: Export library to support IBM XSL (3ced8d73) · Commits · 戴 / test

arch/powerpc/include/asm/opal-api.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -948,6 +948,7 @@ enum {
		OPAL_PHB_CAPI_MODE_SNOOP_OFF = 2,
		OPAL_PHB_CAPI_MODE_SNOOP_ON = 3,
		OPAL_PHB_CAPI_MODE_DMA = 4,
		OPAL_PHB_CAPI_MODE_DMA_TVT1 = 5,
		};

		/* OPAL I2C request */

drivers/misc/cxl/Kconfig

+5 −0

Original line number	Diff line number	Diff line
		@@ -11,11 +11,16 @@ config CXL_AFU_DRIVER_OPS
		bool
		default n

		config CXL_LIB
		bool
		default n

		config CXL
		tristate "Support for IBM Coherent Accelerators (CXL)"
		depends on PPC_POWERNV && PCI_MSI && EEH
		select CXL_BASE
		select CXL_AFU_DRIVER_OPS
		select CXL_LIB
		default m
		help
		Select this option to enable driver support for IBM Coherent

drivers/misc/cxl/Makefile

+1 −1

Original line number	Diff line number	Diff line
		@@ -3,7 +3,7 @@ ccflags-$(CONFIG_PPC_WERROR) += -Werror

		cxl-y += main.o file.o irq.o fault.o native.o
		cxl-y += context.o sysfs.o pci.o trace.o
		cxl-y += vphb.o phb.o api.o
		cxl-y += vphb.o phb.o api.o cxllib.o
		cxl-$(CONFIG_PPC_PSERIES) += flash.o guest.o of.o hcalls.o
		cxl-$(CONFIG_DEBUG_FS) += debugfs.o
		obj-$(CONFIG_CXL) += cxl.o

drivers/misc/cxl/cxl.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -1010,6 +1010,7 @@ static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct den

		void cxl_handle_fault(struct work_struct *work);
		void cxl_prefault(struct cxl_context *ctx, u64 wed);
		int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);

		struct cxl *get_cxl_adapter(int num);
		int cxl_alloc_sst(struct cxl_context *ctx);
		@@ -1061,6 +1062,11 @@ int cxl_afu_slbia(struct cxl_afu *afu);
		int cxl_data_cache_flush(struct cxl *adapter);
		int cxl_afu_disable(struct cxl_afu *afu);
		int cxl_psl_purge(struct cxl_afu *afu);
		int cxl_calc_capp_routing(struct pci_dev dev, u64 chipid,
		u32 phb_index, u64 capp_unit_id);
		int cxl_slot_is_switched(struct pci_dev *dev);
		int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg);
		u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);

		void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
		void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);

drivers/misc/cxl/cxllib.c

0 → 100644

+246 −0

Original line number	Diff line number	Diff line
		/*
		* Copyright 2017 IBM Corp.
		*
		* This program is free software; you can redistribute it and/or
		* modify it under the terms of the GNU General Public License
		* as published by the Free Software Foundation; either version
		* 2 of the License, or (at your option) any later version.
		*/

		#include <linux/hugetlb.h>
		#include <linux/sched/mm.h>
		#include <asm/pnv-pci.h>
		#include <misc/cxllib.h>

		#include "cxl.h"

		#define CXL_INVALID_DRA ~0ull
		#define CXL_DUMMY_READ_SIZE 128
		#define CXL_DUMMY_READ_ALIGN 8
		#define CXL_CAPI_WINDOW_START 0x2000000000000ull
		#define CXL_CAPI_WINDOW_LOG_SIZE 48
		#define CXL_XSL_CONFIG_CURRENT_VERSION CXL_XSL_CONFIG_VERSION1


		bool cxllib_slot_is_supported(struct pci_dev *dev, unsigned long flags)
		{
		int rc;
		u32 phb_index;
		u64 chip_id, capp_unit_id;

		/* No flags currently supported */
		if (flags)
		return false;

		if (!cpu_has_feature(CPU_FTR_HVMODE))
		return false;

		if (!cxl_is_power9())
		return false;

		if (cxl_slot_is_switched(dev))
		return false;

		/* on p9, some pci slots are not connected to a CAPP unit */
		rc = cxl_calc_capp_routing(dev, &chip_id, &phb_index, &capp_unit_id);
		if (rc)
		return false;

		return true;
		}
		EXPORT_SYMBOL_GPL(cxllib_slot_is_supported);

		static DEFINE_MUTEX(dra_mutex);
		static u64 dummy_read_addr = CXL_INVALID_DRA;

		static int allocate_dummy_read_buf(void)
		{
		u64 buf, vaddr;
		size_t buf_size;

		/*
		* Dummy read buffer is 128-byte long, aligned on a
		* 256-byte boundary and we need the physical address.
		*/
		buf_size = CXL_DUMMY_READ_SIZE + (1ull << CXL_DUMMY_READ_ALIGN);
		buf = (u64) kzalloc(buf_size, GFP_KERNEL);
		if (!buf)
		return -ENOMEM;

		vaddr = (buf + (1ull << CXL_DUMMY_READ_ALIGN) - 1) &
		(~0ull << CXL_DUMMY_READ_ALIGN);

		WARN((vaddr + CXL_DUMMY_READ_SIZE) > (buf + buf_size),
		"Dummy read buffer alignment issue");
		dummy_read_addr = virt_to_phys((void *) vaddr);
		return 0;
		}

		int cxllib_get_xsl_config(struct pci_dev dev, struct cxllib_xsl_config cfg)
		{
		int rc;
		u32 phb_index;
		u64 chip_id, capp_unit_id;

		if (!cpu_has_feature(CPU_FTR_HVMODE))
		return -EINVAL;

		mutex_lock(&dra_mutex);
		if (dummy_read_addr == CXL_INVALID_DRA) {
		rc = allocate_dummy_read_buf();
		if (rc) {
		mutex_unlock(&dra_mutex);
		return rc;
		}
		}
		mutex_unlock(&dra_mutex);

		rc = cxl_calc_capp_routing(dev, &chip_id, &phb_index, &capp_unit_id);
		if (rc)
		return rc;

		rc = cxl_get_xsl9_dsnctl(capp_unit_id, &cfg->dsnctl);
		if (rc)
		return rc;
		if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
		/* workaround for DD1 - nbwind = capiind */
		cfg->dsnctl \|= ((u64)0x02 << (63-47));
		}

		cfg->version = CXL_XSL_CONFIG_CURRENT_VERSION;
		cfg->log_bar_size = CXL_CAPI_WINDOW_LOG_SIZE;
		cfg->bar_addr = CXL_CAPI_WINDOW_START;
		cfg->dra = dummy_read_addr;
		return 0;
		}
		EXPORT_SYMBOL_GPL(cxllib_get_xsl_config);

		int cxllib_switch_phb_mode(struct pci_dev *dev, enum cxllib_mode mode,
		unsigned long flags)
		{
		int rc = 0;

		if (!cpu_has_feature(CPU_FTR_HVMODE))
		return -EINVAL;

		switch (mode) {
		case CXL_MODE_PCI:
		/*
		* We currently don't support going back to PCI mode
		* However, we'll turn the invalidations off, so that
		* the firmware doesn't have to ack them and can do
		* things like reset, etc.. with no worries.
		* So always return EPERM (can't go back to PCI) or
		* EBUSY if we couldn't even turn off snooping
		*/
		rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_OFF);
		if (rc)
		rc = -EBUSY;
		else
		rc = -EPERM;
		break;
		case CXL_MODE_CXL:
		/* DMA only supported on TVT1 for the time being */
		if (flags != CXL_MODE_DMA_TVT1)
		return -EINVAL;
		rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_DMA_TVT1);
		if (rc)
		return rc;
		rc = pnv_phb_to_cxl_mode(dev, OPAL_PHB_CAPI_MODE_SNOOP_ON);
		break;
		default:
		rc = -EINVAL;
		}
		return rc;
		}
		EXPORT_SYMBOL_GPL(cxllib_switch_phb_mode);

		/*
		* When switching the PHB to capi mode, the TVT#1 entry for
		* the Partitionable Endpoint is set in bypass mode, like
		* in PCI mode.
		* Configure the device dma to use TVT#1, which is done
		* by calling dma_set_mask() with a mask large enough.
		*/
		int cxllib_set_device_dma(struct pci_dev *dev, unsigned long flags)
		{
		int rc;

		if (flags)
		return -EINVAL;

		rc = dma_set_mask(&dev->dev, DMA_BIT_MASK(64));
		return rc;
		}
		EXPORT_SYMBOL_GPL(cxllib_set_device_dma);

		int cxllib_get_PE_attributes(struct task_struct *task,
		unsigned long translation_mode,
		struct cxllib_pe_attributes *attr)
		{
		struct mm_struct *mm = NULL;

		if (translation_mode != CXL_TRANSLATED_MODE &&
		translation_mode != CXL_REAL_MODE)
		return -EINVAL;

		attr->sr = cxl_calculate_sr(false,
		task == NULL,
		translation_mode == CXL_REAL_MODE,
		true);
		attr->lpid = mfspr(SPRN_LPID);
		if (task) {
		mm = get_task_mm(task);
		if (mm == NULL)
		return -EINVAL;
		/*
		* Caller is keeping a reference on mm_users for as long
		* as XSL uses the memory context
		*/
		attr->pid = mm->context.id;
		mmput(mm);
		} else {
		attr->pid = 0;
		}
		attr->tid = 0;
		return 0;
		}
		EXPORT_SYMBOL_GPL(cxllib_get_PE_attributes);

		int cxllib_handle_fault(struct mm_struct *mm, u64 addr, u64 size, u64 flags)
		{
		int rc;
		u64 dar;
		struct vm_area_struct *vma = NULL;
		unsigned long page_size;

		if (mm == NULL)
		return -EFAULT;

		down_read(&mm->mmap_sem);

		for (dar = addr; dar < addr + size; dar += page_size) {
		if (!vma \|\| dar < vma->vm_start \|\| dar > vma->vm_end) {
		vma = find_vma(mm, addr);
		if (!vma) {
		pr_err("Can't find vma for addr %016llx\n", addr);
		rc = -EFAULT;
		goto out;
		}
		/* get the size of the pages allocated */
		page_size = vma_kernel_pagesize(vma);
		}

		rc = cxl_handle_mm_fault(mm, flags, dar);
		if (rc) {
		pr_err("cxl_handle_mm_fault failed %d", rc);
		rc = -EFAULT;
		goto out;
		}
		}
		rc = 0;
		out:
		up_read(&mm->mmap_sem);
		return rc;
		}
		EXPORT_SYMBOL_GPL(cxllib_handle_fault);

Admin message