Commit 3cb2c996 authored by Yangyang Li's avatar Yangyang Li Committed by Jason Gunthorpe
Browse files

RDMA/hns: Add support for SCCC in size of 64 Bytes 

For HIP09, size of SCCC (Soft Congestion Control Context) is increased to
64 Bytes from 32 Bytes. The hardware will get the configuration of SCCC
from driver instead of using a fixed value.

Link: https://lore.kernel.org/r/1600245806-56321-5-git-send-email-liweihang@huawei.com


Signed-off-by: default avatarYangyang Li <liyangyang20@huawei.com>
Signed-off-by: default avatarWeihang Li <liweihang@huawei.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent 98912ee8

drivers/infiniband/hw/hns/hns_roce_device.h

+1 −1
Original line number Diff line number Diff line
@@ -811,7 +811,7 @@ struct hns_roce_caps { 
	int		irrl_entry_sz;

	int		trrl_entry_sz;

	int		cqc_entry_sz;

	int		sccc_entry_sz;

	int		sccc_sz;

	int		qpc_timer_entry_sz;

	int		cqc_timer_entry_sz;

	int		srqc_entry_sz;

drivers/infiniband/hw/hns/hns_roce_hem.c

+1 −1
Original line number Diff line number Diff line
@@ -1027,7 +1027,7 @@ void hns_roce_cleanup_hem(struct hns_roce_dev *hr_dev) 
	if (hr_dev->caps.cqc_timer_entry_sz)

		hns_roce_cleanup_hem_table(hr_dev,

					   &hr_dev->cqc_timer_table);

	if (hr_dev->caps.sccc_entry_sz)

	if (hr_dev->caps.sccc_sz)

		hns_roce_cleanup_hem_table(hr_dev,

					   &hr_dev->qp_table.sccc_table);

	if (hr_dev->caps.trrl_entry_sz)

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+26 −4
Original line number Diff line number Diff line
@@ -1762,7 +1762,7 @@ static void set_default_caps(struct hns_roce_dev *hr_dev) 
	caps->cqc_timer_buf_pg_sz = 0;

	caps->cqc_timer_hop_num   = HNS_ROCE_HOP_NUM_0;



	caps->sccc_entry_sz	  = HNS_ROCE_V2_SCCC_ENTRY_SZ;

	caps->sccc_sz = HNS_ROCE_V2_SCCC_SZ;

	caps->sccc_ba_pg_sz	  = 0;

	caps->sccc_buf_pg_sz	  = 0;

	caps->sccc_hop_num	  = HNS_ROCE_SCCC_HOP_NUM;
@@ -1872,7 +1872,7 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 
	caps->cqc_entry_sz	     = resp_b->cqc_entry_sz;

	caps->srqc_entry_sz	     = resp_b->srqc_entry_sz;

	caps->idx_entry_sz	     = resp_b->idx_entry_sz;

	caps->sccc_entry_sz	     = resp_b->scc_ctx_entry_sz;

	caps->sccc_sz		     = resp_b->sccc_sz;

	caps->max_mtu		     = resp_b->max_mtu;

	caps->qpc_sz		     = HNS_ROCE_V2_QPC_SZ;

	caps->min_cqes		     = resp_b->min_cqes;
@@ -1997,6 +1997,7 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 
		caps->aeqe_size = HNS_ROCE_V3_EQE_SIZE;

		caps->cqe_sz = HNS_ROCE_V3_CQE_SIZE;

		caps->qpc_sz = HNS_ROCE_V3_QPC_SZ;

		caps->sccc_sz = HNS_ROCE_V3_SCCC_SZ;

	}



	calc_pg_sz(caps->num_qps, caps->qpc_sz, caps->qpc_hop_num,
@@ -2016,7 +2017,7 @@ static int hns_roce_query_pf_caps(struct hns_roce_dev *hr_dev) 
	caps->qpc_timer_hop_num = HNS_ROCE_HOP_NUM_0;

	caps->cqc_timer_hop_num = HNS_ROCE_HOP_NUM_0;



	calc_pg_sz(caps->num_qps, caps->sccc_entry_sz,

	calc_pg_sz(caps->num_qps, caps->sccc_sz,

		   caps->sccc_hop_num, caps->sccc_bt_num,

		   &caps->sccc_buf_pg_sz, &caps->sccc_ba_pg_sz,

		   HEM_TYPE_SCCC);
@@ -2051,6 +2052,21 @@ static int hns_roce_config_qpc_size(struct hns_roce_dev *hr_dev) 
	return hns_roce_cmq_send(hr_dev, &desc, 1);

}



static int hns_roce_config_sccc_size(struct hns_roce_dev *hr_dev)

{

	struct hns_roce_cmq_desc desc;

	struct hns_roce_cfg_entry_size *cfg_size =

				  (struct hns_roce_cfg_entry_size *)desc.data;



	hns_roce_cmq_setup_basic_desc(&desc, HNS_ROCE_OPC_CFG_ENTRY_SIZE,

				      false);



	cfg_size->type = cpu_to_le32(HNS_ROCE_CFG_SCCC_SIZE);

	cfg_size->size = cpu_to_le32(hr_dev->caps.sccc_sz);



	return hns_roce_cmq_send(hr_dev, &desc, 1);

}



static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev)

{

	int ret;
@@ -2059,8 +2075,14 @@ static int hns_roce_config_entry_size(struct hns_roce_dev *hr_dev) 
		return 0;



	ret = hns_roce_config_qpc_size(hr_dev);

	if (ret)

	if (ret) {

		dev_err(hr_dev->dev, "failed to cfg qpc sz, ret = %d.\n", ret);

		return ret;

	}



	ret = hns_roce_config_sccc_size(hr_dev);

	if (ret)

		dev_err(hr_dev->dev, "failed to cfg sccc sz, ret = %d.\n", ret);



	return ret;

}

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+6 −2
Original line number Diff line number Diff line
@@ -85,7 +85,10 @@ 
#define HNS_ROCE_V2_MTPT_ENTRY_SZ		64

#define HNS_ROCE_V2_MTT_ENTRY_SZ		64

#define HNS_ROCE_V2_IDX_ENTRY_SZ		4

#define HNS_ROCE_V2_SCCC_ENTRY_SZ		32



#define HNS_ROCE_V2_SCCC_SZ			32

#define HNS_ROCE_V3_SCCC_SZ			64



#define HNS_ROCE_V2_QPC_TIMER_ENTRY_SZ		PAGE_SIZE

#define HNS_ROCE_V2_CQC_TIMER_ENTRY_SZ		PAGE_SIZE

#define HNS_ROCE_V2_PAGE_SIZE_SUPPORTED		0xFFFFF000
@@ -1544,6 +1547,7 @@ struct hns_roce_cfg_sgid_tb { 


enum {

	HNS_ROCE_CFG_QPC_SIZE = BIT(0),

	HNS_ROCE_CFG_SCCC_SIZE = BIT(1),

};



struct hns_roce_cfg_entry_size {
@@ -1596,7 +1600,7 @@ struct hns_roce_query_pf_caps_b { 
	u8 cqc_entry_sz;

	u8 srqc_entry_sz;

	u8 idx_entry_sz;

	u8 scc_ctx_entry_sz;

	u8 sccc_sz;

	u8 max_mtu;

	__le16 qpc_sz;

	__le16 qpc_timer_entry_sz;

drivers/infiniband/hw/hns/hns_roce_main.c

+3 −3
Original line number Diff line number Diff line
@@ -642,11 +642,11 @@ static int hns_roce_init_hem(struct hns_roce_dev *hr_dev) 
		}

	}



	if (hr_dev->caps.sccc_entry_sz) {

	if (hr_dev->caps.sccc_sz) {

		ret = hns_roce_init_hem_table(hr_dev,

					      &hr_dev->qp_table.sccc_table,

					      HEM_TYPE_SCCC,

					      hr_dev->caps.sccc_entry_sz,

					      hr_dev->caps.sccc_sz,

					      hr_dev->caps.num_qps, 1);

		if (ret) {

			dev_err(dev,
@@ -686,7 +686,7 @@ err_unmap_qpc_timer: 
		hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);



err_unmap_ctx:

	if (hr_dev->caps.sccc_entry_sz)

	if (hr_dev->caps.sccc_sz)

		hns_roce_cleanup_hem_table(hr_dev,

					   &hr_dev->qp_table.sccc_table);

err_unmap_srq:

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