i40e: remove unused defines

		(((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)

#define I40E_DEFAULT_QUEUES_PER_VF	4

#define I40E_MAX_VF_QUEUES		16

#define I40E_DEFAULT_QUEUES_PER_TC	1 /* should be a power of 2 */

#define i40e_pf_get_max_q_per_tc(pf) \

		(((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)

#define I40E_FDIR_RING			0

#define I40E_FDIR_RING_COUNT		32

#define I40E_MAX_AQ_BUF_SIZE		4096

#define I40E_AQ_LEN			256

#define I40E_AQ_WORK_LIMIT		66 /* max number of VFs + a little */

#define I40E_MAX_USER_PRIORITY		8

#define I40E_DEFAULT_TRAFFIC_CLASS	BIT(0)

#define I40E_DEFAULT_MSG_ENABLE		4

#define I40E_QUEUE_WAIT_RETRY_LIMIT	10

#define I40E_INT_NAME_STR_LEN		(IFNAMSIZ + 16)

#define I40E_OEM_SNAP_SHIFT		16

#define I40E_OEM_RELEASE_MASK		0x0000ffff

/* The values in here are decimal coded as hex as is the case in the NVM map*/

#define I40E_CURRENT_NVM_VERSION_HI	0x2

#define I40E_CURRENT_NVM_VERSION_LO	0x40

#define I40E_RX_DESC(R, i)	\

	(&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))

#define I40E_TX_DESC(R, i)	\

#define I40E_TX_FDIRDESC(R, i)	\

	(&(((struct i40e_filter_program_desc *)((R)->desc))[i]))

/* default to trying for four seconds */

#define I40E_TRY_LINK_TIMEOUT	(4 * HZ)

/* BW rate limiting */

#define I40E_BW_CREDIT_DIVISOR		50 /* 50Mbps per BW credit */

#define I40E_BW_MBPS_DIVISOR		125000 /* rate / (1000000 / 8) Mbps */

	u8 tunnel_type;

};

#define I40E_DCB_PRIO_TYPE_STRICT	0

#define I40E_DCB_PRIO_TYPE_ETS		1

#define I40E_DCB_STRICT_PRIO_CREDITS	127

/* DCB per TC information data structure */

struct i40e_tc_info {

	u16	qoffset;	/* Queue offset from base queue */

					     I40E_FLEX_SET_FSIZE(fsize) | \

					     I40E_FLEX_SET_SRC_WORD(src))

#define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \

				     I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \

				     I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)

#define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \

				     I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \

				     I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)

#define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \

				       I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \

				       I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)

#define I40E_MAX_FLEX_SRC_OFFSET 0x1F

#define I40E_L4_GLQF_ORT_IDX		35

/* Flex PIT register index */

#define I40E_FLEX_PIT_IDX_START_L2	0

#define I40E_FLEX_PIT_IDX_START_L3	3

#define I40E_FLEX_PIT_IDX_START_L4	6

#define I40E_HW_GENEVE_OFFLOAD_CAPABLE		BIT(9)

#define I40E_HW_PTP_L4_CAPABLE			BIT(10)

#define I40E_HW_WOL_MC_MAGIC_PKT_WAKE		BIT(11)

#define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE	BIT(12)

#define I40E_HW_HAVE_CRT_RETIMER		BIT(13)

#define I40E_HW_OUTER_UDP_CSUM_CAPABLE		BIT(14)

#define I40E_HW_PHY_CONTROLS_LEDS		BIT(15)

	return gpio_val;

}

#define I40E_COMBINED_ACTIVITY 0xA

#define I40E_FILTER_ACTIVITY 0xE

#define I40E_LINK_ACTIVITY 0xC

#define I40E_MAC_ACTIVITY 0xD

#define I40E_FW_LED BIT(4)

#define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \

			     I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)

#include "i40e_type.h"

#define I40E_DCBX_STATUS_NOT_STARTED	0

#define I40E_DCBX_STATUS_IN_PROGRESS	1

#define I40E_DCBX_STATUS_DONE		2

#define I40E_DCBX_STATUS_MULTIPLE_PEERS	3

#define I40E_DCBX_STATUS_DISABLED	7

#define I40E_TLV_TYPE_END		0

#define I40E_CEE_DCBX_OUI		0x001b21

#define I40E_CEE_DCBX_TYPE		2

#define I40E_CEE_SUBTYPE_CTRL		1

#define I40E_CEE_SUBTYPE_PG_CFG		2

#define I40E_CEE_SUBTYPE_PFC_CFG	3

#define I40E_CEE_SUBTYPE_APP_PRI	4

struct i40e_cee_feat_tlv {

	struct i40e_cee_tlv_hdr hdr;

	u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */

#define I40E_CEE_FEAT_TLV_ENABLE_MASK	0x80

#define I40E_CEE_FEAT_TLV_WILLING_MASK	0x40

#define I40E_CEE_FEAT_TLV_ERR_MASK	0x20

	u8 subtype;

	u8 tlvinfo[1];

};

			i40e_dbg_dump_vf(pf, i);

}

#define I40E_MAX_DEBUG_OUT_BUFFER (4096*4)

/**

 * i40e_dbg_command_write - write into command datum

 * @filp: the opened file