Commit 3c772f71 authored by Takeshi Kihara's avatar Takeshi Kihara Committed by Geert Uytterhoeven
Browse files

clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC 



The clock sources of the AXI BUS clock (266.66 MHz) used for SYS-DMAC
DMA transfers are:

    Channel      R-Car H3    R-Car M3-W    R-Car M3-N
    -------------------------------------------------
    SYS-DMAC0    S0D3        S0D3          S0D3
    SYS-DMAC1    S3D1        S3D1          S3D1
    SYS-DMAC2    S3D1        S3D1          S3D1

As a result, change the parent clocks of the SYS-DMAC{1,2} module clocks
on R-Car H3, R-Car M3-W, and R-Car M3-N to S3D1.

NOTE: This information will be reflected in a future revision of the
      R-Car Gen3 Hardware Manual.

Signed-off-by: default avatarTakeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update RZ/G2M]
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent c2182095

drivers/clk/renesas/r8a774a1-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -123,8 +123,8 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = { 
	DEF_MOD("msiof2",		 209,	R8A774A1_CLK_MSO),

	DEF_MOD("msiof1",		 210,	R8A774A1_CLK_MSO),

	DEF_MOD("msiof0",		 211,	R8A774A1_CLK_MSO),

	DEF_MOD("sys-dmac2",		 217,	R8A774A1_CLK_S0D3),

	DEF_MOD("sys-dmac1",		 218,	R8A774A1_CLK_S0D3),

	DEF_MOD("sys-dmac2",		 217,	R8A774A1_CLK_S3D1),

	DEF_MOD("sys-dmac1",		 218,	R8A774A1_CLK_S3D1),

	DEF_MOD("sys-dmac0",		 219,	R8A774A1_CLK_S0D3),

	DEF_MOD("cmt3",			 300,	R8A774A1_CLK_R),

	DEF_MOD("cmt2",			 301,	R8A774A1_CLK_R),

drivers/clk/renesas/r8a7795-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -130,8 +130,8 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = { 
	DEF_MOD("msiof2",		 209,	R8A7795_CLK_MSO),

	DEF_MOD("msiof1",		 210,	R8A7795_CLK_MSO),

	DEF_MOD("msiof0",		 211,	R8A7795_CLK_MSO),

	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S0D3),

	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S0D3),

	DEF_MOD("sys-dmac2",		 217,	R8A7795_CLK_S3D1),

	DEF_MOD("sys-dmac1",		 218,	R8A7795_CLK_S3D1),

	DEF_MOD("sys-dmac0",		 219,	R8A7795_CLK_S0D3),

	DEF_MOD("sceg-pub",		 229,	R8A7795_CLK_CR),

	DEF_MOD("cmt3",			 300,	R8A7795_CLK_R),

drivers/clk/renesas/r8a7796-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -127,8 +127,8 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("msiof2",		 209,	R8A7796_CLK_MSO),

	DEF_MOD("msiof1",		 210,	R8A7796_CLK_MSO),

	DEF_MOD("msiof0",		 211,	R8A7796_CLK_MSO),

	DEF_MOD("sys-dmac2",		 217,	R8A7796_CLK_S0D3),

	DEF_MOD("sys-dmac1",		 218,	R8A7796_CLK_S0D3),

	DEF_MOD("sys-dmac2",		 217,	R8A7796_CLK_S3D1),

	DEF_MOD("sys-dmac1",		 218,	R8A7796_CLK_S3D1),

	DEF_MOD("sys-dmac0",		 219,	R8A7796_CLK_S0D3),

	DEF_MOD("cmt3",			 300,	R8A7796_CLK_R),

	DEF_MOD("cmt2",			 301,	R8A7796_CLK_R),

drivers/clk/renesas/r8a77965-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -123,8 +123,8 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = { 
	DEF_MOD("msiof2",		209,	R8A77965_CLK_MSO),

	DEF_MOD("msiof1",		210,	R8A77965_CLK_MSO),

	DEF_MOD("msiof0",		211,	R8A77965_CLK_MSO),

	DEF_MOD("sys-dmac2",		217,	R8A77965_CLK_S0D3),

	DEF_MOD("sys-dmac1",		218,	R8A77965_CLK_S0D3),

	DEF_MOD("sys-dmac2",		217,	R8A77965_CLK_S3D1),

	DEF_MOD("sys-dmac1",		218,	R8A77965_CLK_S3D1),

	DEF_MOD("sys-dmac0",		219,	R8A77965_CLK_S0D3),



	DEF_MOD("cmt3",			300,	R8A77965_CLK_R),

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