Commit 3c4c9b81 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: BDW needs D_COMP writes through MCHBAR 



That's what the spec said! And HSW needs it through pcode (you can
only read it through MCHBAR), so create hsw_write_dcomp to abstract
the weirdness.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 414de7a0

drivers/gpu/drm/i915/intel_display.c

+18 −10
Original line number Diff line number Diff line
@@ -6885,6 +6885,22 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) 
	spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);

}



static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)

{

	struct drm_device *dev = dev_priv->dev;



	if (IS_HASWELL(dev)) {

		mutex_lock(&dev_priv->rps.hw_lock);

		if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,

					    val))

			DRM_ERROR("Failed to disable D_COMP\n");

		mutex_unlock(&dev_priv->rps.hw_lock);

	} else {

		I915_WRITE(D_COMP, val);

	}

	POSTING_READ(D_COMP);

}



/*

 * This function implements pieces of two sequences from BSpec:

 * - Sequence for display software to disable LCPLL
@@ -6922,11 +6938,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, 


	val = I915_READ(D_COMP);

	val |= D_COMP_COMP_DISABLE;

	mutex_lock(&dev_priv->rps.hw_lock);

	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))

		DRM_ERROR("Failed to disable D_COMP\n");

	mutex_unlock(&dev_priv->rps.hw_lock);

	POSTING_READ(D_COMP);

	hsw_write_dcomp(dev_priv, val);

	ndelay(100);



	if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
@@ -6981,11 +6993,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) 
	val = I915_READ(D_COMP);

	val |= D_COMP_COMP_FORCE;

	val &= ~D_COMP_COMP_DISABLE;

	mutex_lock(&dev_priv->rps.hw_lock);

	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))

		DRM_ERROR("Failed to enable D_COMP\n");

	mutex_unlock(&dev_priv->rps.hw_lock);

	POSTING_READ(D_COMP);

	hsw_write_dcomp(dev_priv, val);



	val = I915_READ(LCPLL_CTL);

	val &= ~LCPLL_PLL_DISABLE;

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