drm/nouveau/gr/gv100-: modify gr init to match newer version of RM (3c47e381) · Commits · 戴 / test

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c

+3 −9

Original line number	Diff line number	Diff line
		@@ -1324,10 +1324,8 @@ gf100_grctx_generate_sm_id(struct gf100_gr *gr, int gpc, int tpc, int sm)
		void
		gf100_grctx_generate_floorsweep(struct gf100_gr *gr)
		{
		struct nvkm_device *device = gr->base.engine.subdev.device;
		const struct gf100_grctx_func *func = gr->func->grctx;
		int gpc, sm, i, j;
		u32 data;
		int sm;

		for (sm = 0; sm < gr->sm_nr; sm++) {
		func->sm_id(gr, gr->sm[sm].gpc, gr->sm[sm].tpc, sm);
		@@ -1335,12 +1333,8 @@ gf100_grctx_generate_floorsweep(struct gf100_gr *gr)
		func->tpc_nr(gr, gr->sm[sm].gpc);
		}

		for (gpc = 0, i = 0; i < 4; i++) {
		for (data = 0, j = 0; j < 8 && gpc < gr->gpc_nr; j++, gpc++)
		data \|= gr->tpc_nr[gpc] << (j * 4);
		nvkm_wr32(device, 0x406028 + (i * 4), data);
		nvkm_wr32(device, 0x405870 + (i * 4), data);
		}
		gf100_gr_init_num_tpc_per_gpc(gr, false, true);
		gf100_gr_init_num_tpc_per_gpc(gr, true, false);

		if (func->r4060a8)
		func->r4060a8(gr);

+5 −6

Original line number	Diff line number	Diff line
		@@ -67,14 +67,14 @@ gv100_grctx_generate_attrib(struct gf100_grctx *info)
		const u32 attrib = grctx->attrib_nr;
		const u32 gfxp = grctx->gfxp_nr;
		const int s = 12;
		const int max_batches = 0xffff;
		u32 size = grctx->alpha_nr_max * gr->tpc_total;
		u32 ao = 0;
		u32 bo = ao + size;
		int gpc, ppc, b, n = 0;

		size += grctx->gfxp_nr * gr->tpc_total;
		size = ((size * 0x20) + 128) & ~127;
		for (gpc = 0; gpc < gr->gpc_nr; gpc++)
		size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max;
		size = ((size * 0x20) + 127) & ~127;
		b = mmio_vram(info, size, (1 << s), false);

		mmio_refn(info, 0x418810, 0x80000000, s, b);
		@@ -84,13 +84,12 @@ gv100_grctx_generate_attrib(struct gf100_grctx *info)
		mmio_wr32(info, 0x419e04, 0x80000000 \| size >> 7);
		mmio_wr32(info, 0x405830, attrib);
		mmio_wr32(info, 0x40585c, alpha);
		mmio_wr32(info, 0x4064c4, ((alpha / 4) << 16) \| max_batches);

		for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
		for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
		const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
		const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc];
		const u32 gs = gfxp * gr->ppc_tpc_nr[gpc][ppc];
		const u32 bs = attrib * gr->ppc_tpc_max;
		const u32 gs = gfxp * gr->ppc_tpc_max;
		const u32 u = 0x418ea0 + (n * 0x04);
		const u32 o = PPC_UNIT(gpc, ppc, 0);
		if (!(gr->ppc_mask[gpc] & (1 << ppc)))

+18 −1

Original line number	Diff line number	Diff line
		@@ -2169,6 +2169,23 @@ gf100_gr_new_(const struct gf100_gr_func func, struct nvkm_device device,
		return 0;
		}

		void
		gf100_gr_init_num_tpc_per_gpc(struct gf100_gr *gr, bool pd, bool ds)
		{
		struct nvkm_device *device = gr->base.engine.subdev.device;
		int gpc, i, j;
		u32 data;

		for (gpc = 0, i = 0; i < 4; i++) {
		for (data = 0, j = 0; j < 8 && gpc < gr->gpc_nr; j++, gpc++)
		data \|= gr->tpc_nr[gpc] << (j * 4);
		if (pd)
		nvkm_wr32(device, 0x406028 + (i * 4), data);
		if (ds)
		nvkm_wr32(device, 0x405870 + (i * 4), data);
		}
		}

		void
		gf100_gr_init_400054(struct gf100_gr *gr)
		{
		@@ -2336,8 +2353,8 @@ gf100_gr_init(struct gf100_gr *gr)
		if (gr->func->init_40601c)
		gr->func->init_40601c(gr);

		nvkm_wr32(device, 0x404490, 0xc0000000);
		nvkm_wr32(device, 0x406018, 0xc0000000);
		nvkm_wr32(device, 0x404490, 0xc0000000);

		if (gr->func->init_sked_hww_esr)
		gr->func->init_sked_hww_esr(gr);

+1 −0

Original line number	Diff line number	Diff line
		@@ -216,6 +216,7 @@ void gf100_gr_init_419eb4(struct gf100_gr *);
		void gf100_gr_init_tex_hww_esr(struct gf100_gr *, int, int);
		void gf100_gr_init_shader_exceptions(struct gf100_gr *, int, int);
		void gf100_gr_init_400054(struct gf100_gr *);
		void gf100_gr_init_num_tpc_per_gpc(struct gf100_gr *, bool, bool);
		extern const struct gf100_gr_func_zbc gf100_gr_zbc;

		void gf117_gr_init_zcull(struct gf100_gr *);