Commit 3c45d751 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'powerpc-5.5-6' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux 

Pull powerpc fixes from Michael Ellerman:
 "Some more powerpc fixes for 5.5:

   - Fix our hash MMU code to avoid having overlapping ids between user
     and kernel, which isn't as bad as it sounds but led to crashes on
     some machines.

   - A fix for the Power9 XIVE interrupt code, which could return the
     wrong interrupt state in obscure error conditions.

   - A minor Kconfig fix for the recently added CONFIG_PPC_UV code.

  Thanks to Aneesh Kumar K.V, Bharata B Rao, Cédric Le Goater, Frederic
  Barrat"

* tag 'powerpc-5.5-6' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux:
  powerpc/mm/hash: Fix sharing context ids between kernel & userspace
  powerpc/xive: Discard ESB load value when interrupt is invalid
  powerpc: Ultravisor: Fix the dependencies for CONFIG_PPC_UV
parents 274adbff 5d2e5dd5

arch/powerpc/Kconfig

+1 −5
Original line number Diff line number Diff line
@@ -455,11 +455,7 @@ config PPC_TRANSACTIONAL_MEM 
config PPC_UV

	bool "Ultravisor support"

	depends on KVM_BOOK3S_HV_POSSIBLE

	select ZONE_DEVICE

	select DEV_PAGEMAP_OPS

	select DEVICE_PRIVATE

	select MEMORY_HOTPLUG

	select MEMORY_HOTREMOVE

	depends on DEVICE_PRIVATE

	default n

	help

	  This option paravirtualizes the kernel to run in POWER platforms that

arch/powerpc/include/asm/book3s/64/mmu-hash.h

+4 −1
Original line number Diff line number Diff line
@@ -600,8 +600,11 @@ extern void slb_set_size(u16 size); 
 *

 */

#define MAX_USER_CONTEXT	((ASM_CONST(1) << CONTEXT_BITS) - 2)



// The + 2 accounts for INVALID_REGION and 1 more to avoid overlap with kernel

#define MIN_USER_CONTEXT	(MAX_KERNEL_CTX_CNT + MAX_VMALLOC_CTX_CNT + \

				 MAX_IO_CTX_CNT + MAX_VMEMMAP_CTX_CNT)

				 MAX_IO_CTX_CNT + MAX_VMEMMAP_CTX_CNT + 2)



/*

 * For platforms that support on 65bit VA we limit the context bits

 */

arch/powerpc/include/asm/xive-regs.h

+1 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 


#define XIVE_ESB_VAL_P		0x2

#define XIVE_ESB_VAL_Q		0x1

#define XIVE_ESB_INVALID	0xFF



/*

 * Thread Management (aka "TM") registers

arch/powerpc/sysdev/xive/common.c

+12 −3
Original line number Diff line number Diff line
@@ -972,12 +972,21 @@ static int xive_get_irqchip_state(struct irq_data *data, 
				  enum irqchip_irq_state which, bool *state)

{

	struct xive_irq_data *xd = irq_data_get_irq_handler_data(data);

	u8 pq;



	switch (which) {

	case IRQCHIP_STATE_ACTIVE:

		*state = !xd->stale_p &&

			 (xd->saved_p ||

			  !!(xive_esb_read(xd, XIVE_ESB_GET) & XIVE_ESB_VAL_P));

		pq = xive_esb_read(xd, XIVE_ESB_GET);



		/*

		 * The esb value being all 1's means we couldn't get

		 * the PQ state of the interrupt through mmio. It may

		 * happen, for example when querying a PHB interrupt

		 * while the PHB is in an error state. We consider the

		 * interrupt to be inactive in that case.

		 */

		*state = (pq != XIVE_ESB_INVALID) && !xd->stale_p &&

			(xd->saved_p || !!(pq & XIVE_ESB_VAL_P));

		return 0;

	default:

		return -EINVAL;

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