ARM: exynos: Remove static mapping of SCU SFR (3c33710b) · Commits · 戴 / test

arch/arm/mach-exynos/common.h

+5 −0

Original line number	Diff line number	Diff line
		@@ -141,6 +141,11 @@ extern void exynos_cpu_restore_register(void);
		extern void exynos_pm_central_suspend(void);
		extern int exynos_pm_central_resume(void);
		extern void exynos_enter_aftr(void);
		#ifdef CONFIG_SMP
		extern void exynos_scu_enable(void);
		#else
		static inline void exynos_scu_enable(void) { }
		#endif

		extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;

+0 −22

Original line number	Diff line number	Diff line
		@@ -24,15 +24,6 @@

		#include "common.h"

		static struct map_desc exynos4_iodesc[] __initdata = {
		{
		.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
		.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
		.length = SZ_8K,
		.type = MT_DEVICE,
		},
		};

		static struct platform_device exynos_cpuidle = {
		.name = "exynos_cpuidle",
		#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
		@@ -85,17 +76,6 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
		return 1;
		}

		/*
		* exynos_map_io
		*
		* register the standard cpu IO areas
		*/
		static void __init exynos_map_io(void)
		{
		if (soc_is_exynos4())
		iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
		}

		static void __init exynos_init_io(void)
		{
		debug_ll_io_init();
		@@ -104,8 +84,6 @@ static void __init exynos_init_io(void)

		/* detect cpu id and rev. */
		s5p_init_cpu(S5P_VA_CHIPID);

		exynos_map_io();
		}

		/*

+0 −2

+21 −6

Original line number	Diff line number	Diff line
		@@ -163,6 +163,26 @@ int exynos_cluster_power_state(int cluster)
		S5P_CORE_LOCAL_PWR_EN);
		}

		/**
		* exynos_scu_enable : enables SCU for Cortex-A9 based system
		*/
		void exynos_scu_enable(void)
		{
		struct device_node *np;
		static void __iomem *scu_base;

		if (!scu_base) {
		np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
		if (np) {
		scu_base = of_iomap(np, 0);
		of_node_put(np);
		} else {
		scu_base = ioremap(scu_a9_get_base(), SZ_4K);
		}
		}
		scu_enable(scu_base);
		}

		static void __iomem *cpu_boot_reg_base(void)
		{
		if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
		@@ -219,11 +239,6 @@ static void write_pen_release(int val)
		sync_cache_w(&pen_release);
		}

		static void __iomem *scu_base_addr(void)
		{
		return (void __iomem *)(S5P_VA_SCU);
		}

		static DEFINE_SPINLOCK(boot_lock);

		static void exynos_secondary_init(unsigned int cpu)
		@@ -389,7 +404,7 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
		exynos_set_delayed_reset_assertion(true);

		if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
		scu_enable(scu_base_addr());
		exynos_scu_enable();

		/*
		* Write the address of secondary startup into the

+1 −3

Original line number	Diff line number	Diff line
		@@ -22,8 +22,6 @@
		#include <asm/suspend.h>
		#include <asm/cacheflush.h>

		#include <mach/map.h>

		#include "common.h"

		static inline void __iomem *exynos_boot_vector_addr(void)
		@@ -172,7 +170,7 @@ void exynos_enter_aftr(void)
		cpu_suspend(0, exynos_aftr_finisher);

		if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
		scu_enable(S5P_VA_SCU);
		exynos_scu_enable();
		if (call_firmware_op(resume) == -ENOSYS)
		exynos_cpu_restore_register();
		}