perf vendor events powerpc: Update POWER9 events (3c22ba52) · Commits · 戴 / test

tools/perf/pmu-events/arch/powerpc/power9/cache.json

+76 −115

Original line number	Diff line number	Diff line
		[
		{,
		"EventCode": "0x1002A",
		"EventName": "PM_CMPLU_STALL_LARX",
		"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied",
		"PublicDescription": ""
		"EventCode": "0x300F4",
		"EventName": "PM_THRD_CONC_RUN_INST",
		"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set"
		},
		{,
		"EventCode": "0x1003C",
		"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
		"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
		"PublicDescription": ""
		"EventCode": "0x1E056",
		"EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
		"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion"
		},
		{,
		"EventCode": "0x14048",
		"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
		"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)",
		"PublicDescription": ""
		"EventCode": "0x4D016",
		"EventName": "PM_CMPLU_STALL_FXLONG",
		"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)"
		},
		{,
		"EventCode": "0x3E054",
		"EventName": "PM_LD_MISS_L1",
		"BriefDescription": "Load Missed L1, counted at execution time (can be greater than loads finished). LMQ merges are not included in this count. i.e. if a load instruction misses on an address that is already allocated on the LMQ, this event will not increment for that load). Note that this count is per slice, so if a load spans multiple slices this event will increment multiple times for a single load.",
		"PublicDescription": ""
		"EventCode": "0x2D016",
		"EventName": "PM_CMPLU_STALL_FXU",
		"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes"
		},
		{,
		"EventCode": "0x400F0",
		"EventName": "PM_LD_MISS_L1",
		"BriefDescription": "Load Missed L1, at execution time (not gated by finish, which means this counter can be greater than loads finished)",
		"PublicDescription": ""
		"EventCode": "0x1D15C",
		"EventName": "PM_MRK_DTLB_MISS_1G",
		"BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used"
		},
		{,
		"EventCode": "0x1404A",
		"EventName": "PM_INST_FROM_RL2L3_SHR",
		"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
		"PublicDescription": ""
		"EventCode": "0x4D12A",
		"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
		"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load"
		},
		{,
		"EventCode": "0x1C058",
		"EventName": "PM_DTLB_MISS_16G",
		"BriefDescription": "Data TLB Miss page size 16G",
		"PublicDescription": ""
		"EventCode": "0x1003C",
		"EventName": "PM_CMPLU_STALL_DMISS_L2L3",
		"BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3"
		},
		{,
		"EventCode": "0x1D15C",
		"EventName": "PM_MRK_DTLB_MISS_1G",
		"BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used",
		"PublicDescription": ""
		"EventCode": "0x4C014",
		"EventName": "PM_CMPLU_STALL_LMQ_FULL",
		"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full"
		},
		{,
		"EventCode": "0x1E056",
		"EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD",
		"BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion",
		"PublicDescription": ""
		"EventCode": "0x14048",
		"EventName": "PM_INST_FROM_ON_CHIP_CACHE",
		"BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)"
		},
		{,
		"EventCode": "0x101E6",
		"EventName": "PM_THRESH_EXC_4096",
		"BriefDescription": "Threshold counter exceed a count of 4096",
		"PublicDescription": ""
		"EventCode": "0x4D014",
		"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
		"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish"
		},
		{,
		"EventCode": "0x2C01A",
		"EventName": "PM_CMPLU_STALL_LHS",
		"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data",
		"PublicDescription": ""
		"EventCode": "0x2404A",
		"EventName": "PM_INST_FROM_RL4",
		"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
		},
		{,
		"EventCode": "0x2D016",
		"EventName": "PM_CMPLU_STALL_FXU",
		"BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes",
		"PublicDescription": ""
		"EventCode": "0x1404A",
		"EventName": "PM_INST_FROM_RL2L3_SHR",
		"BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
		},
		{,
		"EventCode": "0x24046",
		"EventName": "PM_INST_FROM_RL2L3_MOD",
		"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)",
		"PublicDescription": ""
		"EventCode": "0x401EA",
		"EventName": "PM_THRESH_EXC_128",
		"BriefDescription": "Threshold counter exceeded a value of 128"
		},
		{,
		"EventCode": "0x2404A",
		"EventName": "PM_INST_FROM_RL4",
		"BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
		"PublicDescription": ""
		"EventCode": "0x400F6",
		"EventName": "PM_BR_MPRED_CMPL",
		"BriefDescription": "Number of Branch Mispredicts"
		},
		{,
		"EventCode": "0x2F140",
		"EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
		"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
		"PublicDescription": ""
		"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
		},
		{,
		"EventCode": "0x2D15E",
		"EventName": "PM_MRK_DTLB_MISS_16G",
		"BriefDescription": "Marked Data TLB Miss page size 16G",
		"PublicDescription": ""
		},
		{,
		"EventCode": "0x3F14A",
		"EventName": "PM_MRK_DPTEG_FROM_RMEM",
		"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included",
		"PublicDescription": ""
		"EventCode": "0x101E6",
		"EventName": "PM_THRESH_EXC_4096",
		"BriefDescription": "Threshold counter exceed a count of 4096"
		},
		{,
		"EventCode": "0x3D156",
		"EventName": "PM_MRK_DTLB_MISS_64K",
		"BriefDescription": "Marked Data TLB Miss page size 64K",
		"PublicDescription": ""
		"BriefDescription": "Marked Data TLB Miss page size 64K"
		},
		{,
		"EventCode": "0x3006C",
		"EventName": "PM_RUN_CYC_SMT2_MODE",
		"BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT2 mode",
		"PublicDescription": ""
		"EventCode": "0x4C15E",
		"EventName": "PM_MRK_DTLB_MISS_16M",
		"BriefDescription": "Marked Data TLB Miss page size 16M"
		},
		{,
		"EventCode": "0x300F4",
		"EventName": "PM_THRD_CONC_RUN_INST",
		"BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set",
		"PublicDescription": ""
		"EventCode": "0x2D15E",
		"EventName": "PM_MRK_DTLB_MISS_16G",
		"BriefDescription": "Marked Data TLB Miss page size 16G"
		},
		{,
		"EventCode": "0x4C014",
		"EventName": "PM_CMPLU_STALL_LMQ_FULL",
		"BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full",
		"PublicDescription": ""
		"EventCode": "0x3F14A",
		"EventName": "PM_MRK_DPTEG_FROM_RMEM",
		"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
		},
		{,
		"EventCode": "0x4C016",
		"EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
		"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
		"PublicDescription": ""
		},
		{,
		"EventCode": "0x4D014",
		"EventName": "PM_CMPLU_STALL_LOAD_FINISH",
		"BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish",
		"PublicDescription": ""
		"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict"
		},
		{,
		"EventCode": "0x4D016",
		"EventName": "PM_CMPLU_STALL_FXLONG",
		"BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)",
		"PublicDescription": ""
		"EventCode": "0x2C01A",
		"EventName": "PM_CMPLU_STALL_LHS",
		"BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data"
		},
		{,
		"EventCode": "0x4D12A",
		"EventName": "PM_MRK_DATA_FROM_RL4_CYC",
		"BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
		"PublicDescription": ""
		"EventCode": "0x401E4",
		"EventName": "PM_MRK_DTLB_MISS",
		"BriefDescription": "Marked dtlb miss"
		},
		{,
		"EventCode": "0x4C15E",
		"EventName": "PM_MRK_DTLB_MISS_16M",
		"BriefDescription": "Marked Data TLB Miss page size 16M",
		"PublicDescription": ""
		"EventCode": "0x24046",
		"EventName": "PM_INST_FROM_RL2L3_MOD",
		"BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)"
		},
		{,
		"EventCode": "0x401E4",
		"EventName": "PM_MRK_DTLB_MISS",
		"BriefDescription": "Marked dtlb miss",
		"PublicDescription": ""
		"EventCode": "0x1002A",
		"EventName": "PM_CMPLU_STALL_LARX",
		"BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied"
		},
		{,
		"EventCode": "0x401EA",
		"EventName": "PM_THRESH_EXC_128",
		"BriefDescription": "Threshold counter exceeded a value of 128",
		"PublicDescription": ""
		"EventCode": "0x3006C",
		"EventName": "PM_RUN_CYC_SMT2_MODE",
		"BriefDescription": "Cycles in which this thread's run latch is set and the core is in SMT2 mode"
		},
		{,
		"EventCode": "0x400F6",
		"EventName": "PM_BR_MPRED_CMPL",
		"BriefDescription": "Number of Branch Mispredicts",
		"PublicDescription": ""
		"EventCode": "0x1C058",
		"EventName": "PM_DTLB_MISS_16G",
		"BriefDescription": "Data TLB Miss page size 16G"
		}
		]
		No newline at end of file

tools/perf/pmu-events/arch/powerpc/power9/floating-point.json

+15 −27

Original line number	Diff line number	Diff line
		[
		{,
		"EventCode": "0x10058",
		"EventName": "PM_MEM_LOC_THRESH_IFU",
		"BriefDescription": "Local Memory above threshold for IFU speculation control",
		"PublicDescription": ""
		},
		{,
		"EventCode": "0x4505E",
		"EventName": "PM_FLOP_CMPL",
		"BriefDescription": "Floating Point Operation Finished",
		"PublicDescription": ""
		},
		{,
		"EventCode": "0x1415A",
		"EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
		"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
		"PublicDescription": ""
		"BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load"
		},
		{,
		"EventCode": "0x2D028",
		"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
		"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache",
		"PublicDescription": ""
		"EventCode": "0x10058",
		"EventName": "PM_MEM_LOC_THRESH_IFU",
		"BriefDescription": "Local Memory above threshold for IFU speculation control"
		},
		{,
		"EventCode": "0x2D154",
		"EventName": "PM_MRK_DERAT_MISS_64K",
		"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K",
		"PublicDescription": ""
		"EventCode": "0x2D028",
		"EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
		"BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache"
		},
		{,
		"EventCode": "0x30012",
		"EventName": "PM_FLUSH_COMPLETION",
		"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush",
		"PublicDescription": ""
		"BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush"
		},
		{,
		"EventCode": "0x2D154",
		"EventName": "PM_MRK_DERAT_MISS_64K",
		"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K"
		},
		{,
		"EventCode": "0x4016E",
		"EventName": "PM_THRESH_NOT_MET",
		"BriefDescription": "Threshold counter did not meet threshold",
		"PublicDescription": ""
		"BriefDescription": "Threshold counter did not meet threshold"
		}
		]
		No newline at end of file

tools/perf/pmu-events/arch/powerpc/power9/frontend.json

+224 −293

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tools/perf/pmu-events/arch/powerpc/power9/marked.json

+385 −520

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tools/perf/pmu-events/arch/powerpc/power9/memory.json

+76 −102

Original line number	Diff line number	Diff line
		[
		{,
		"EventCode": "0x10008",
		"EventName": "PM_RUN_SPURR",
		"BriefDescription": "Run SPURR",
		"PublicDescription": ""
		},
		{,
		"EventCode": "0x1000A",
		"EventName": "PM_PMC3_REWIND",
		"BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change.",
		"PublicDescription": ""
		"EventCode": "0x3006E",
		"EventName": "PM_NEST_REF_CLK",
		"BriefDescription": "Multiply by 4 to obtain the number of PB cycles"
		},
		{,
		"EventCode": "0x1C040",
		"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
		"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load",
		"PublicDescription": ""
		"EventCode": "0x20010",
		"EventName": "PM_PMC1_OVERFLOW",
		"BriefDescription": "Overflow from counter 1"
		},
		{,
		"EventCode": "0x1C050",
		"EventName": "PM_DATA_CHIP_PUMP_CPRED",
		"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load",
		"PublicDescription": ""
		"EventCode": "0x2005A",
		"EventName": "PM_DARQ1_7_9_ENTRIES",
		"BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use"
		},
		{,
		"EventCode": "0x1D15E",
		"EventName": "PM_MRK_RUN_CYC",
		"BriefDescription": "Run cycles in which a marked instruction is in the pipeline",
		"PublicDescription": ""
		"EventCode": "0x3C048",
		"EventName": "PM_DATA_FROM_DL2L3_SHR",
		"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
		},
		{,
		"EventCode": "0x15158",
		"EventName": "PM_SYNC_MRK_L2HIT",
		"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt",
		"PublicDescription": ""
		"EventCode": "0x10008",
		"EventName": "PM_RUN_SPURR",
		"BriefDescription": "Run SPURR"
		},
		{,
		"EventCode": "0x20010",
		"EventName": "PM_PMC1_OVERFLOW",
		"BriefDescription": "Overflow from counter 1",
		"PublicDescription": ""
		"EventCode": "0x200F6",
		"EventName": "PM_LSU_DERAT_MISS",
		"BriefDescription": "DERAT Reloaded due to a DERAT miss"
		},
		{,
		"EventCode": "0x2C040",
		"EventName": "PM_DATA_FROM_L2_MEPF",
		"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load",
		"PublicDescription": ""
		"EventCode": "0x4C048",
		"EventName": "PM_DATA_FROM_DL2L3_MOD",
		"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load"
		},
		{,
		"EventCode": "0x2005A",
		"EventName": "PM_DARQ1_7_9_ENTRIES",
		"BriefDescription": "Cycles in which 7 to 9 DARQ1 entries (out of 12) are in use",
		"PublicDescription": ""
		"EventCode": "0x1D15E",
		"EventName": "PM_MRK_RUN_CYC",
		"BriefDescription": "Run cycles in which a marked instruction is in the pipeline"
		},
		{,
		"EventCode": "0x2C05C",
		"EventName": "PM_INST_GRP_PUMP_CPRED",
		"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)",
		"PublicDescription": ""
		"EventCode": "0x4003E",
		"EventName": "PM_LD_CMPL",
		"BriefDescription": "count of Loads completed"
		},
		{,
		"EventCode": "0x2D156",
		"EventName": "PM_MRK_DTLB_MISS_4K",
		"BriefDescription": "Marked Data TLB Miss page size 4k",
		"PublicDescription": ""
		},
		{,
		"EventCode": "0x2E05A",
		"EventName": "PM_LRQ_REJECT",
		"BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects",
		"PublicDescription": ""
		"BriefDescription": "Marked Data TLB Miss page size 4k"
		},
		{,
		"EventCode": "0x2E05C",
		"EventName": "PM_LSU_REJECT_ERAT_MISS",
		"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)",
		"PublicDescription": ""
		"EventCode": "0x4C042",
		"EventName": "PM_DATA_FROM_L3",
		"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load"
		},
		{,
		"EventCode": "0x200F6",
		"EventName": "PM_LSU_DERAT_MISS",
		"BriefDescription": "DERAT Reloaded due to a DERAT miss",
		"PublicDescription": ""
		"EventCode": "0x4D02C",
		"EventName": "PM_PMC1_REWIND",
		"BriefDescription": ""
		},
		{,
		"EventCode": "0x3C048",
		"EventName": "PM_DATA_FROM_DL2L3_SHR",
		"BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
		"PublicDescription": ""
		"EventCode": "0x15158",
		"EventName": "PM_SYNC_MRK_L2HIT",
		"BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt"
		},
		{,
		"EventCode": "0x3404A",
		"EventName": "PM_INST_FROM_RMEM",
		"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)",
		"PublicDescription": ""
		"BriefDescription": "The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)"
		},
		{,
		"EventCode": "0x3C058",
		"EventName": "PM_LARX_FIN",
		"BriefDescription": "Larx finished",
		"PublicDescription": ""
		"EventCode": "0x301E2",
		"EventName": "PM_MRK_ST_CMPL",
		"BriefDescription": "Marked store completed and sent to nest"
		},
		{,
		"EventCode": "0x3E050",
		"EventName": "PM_DARQ1_4_6_ENTRIES",
		"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use",
		"PublicDescription": ""
		"EventCode": "0x1C050",
		"EventName": "PM_DATA_CHIP_PUMP_CPRED",
		"BriefDescription": "Initial and Final Pump Scope was chip pump (prediction=correct) for a demand load"
		},
		{,
		"EventCode": "0x3006E",
		"EventName": "PM_NEST_REF_CLK",
		"BriefDescription": "Multiply by 4 to obtain the number of PB cycles",
		"PublicDescription": ""
		"EventCode": "0x4C040",
		"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
		"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load"
		},
		{,
		"EventCode": "0x301E2",
		"EventName": "PM_MRK_ST_CMPL",
		"BriefDescription": "Marked store completed and sent to nest",
		"PublicDescription": ""
		"EventCode": "0x2E05C",
		"EventName": "PM_LSU_REJECT_ERAT_MISS",
		"BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)"
		},
		{,
		"EventCode": "0x4D02C",
		"EventName": "PM_PMC1_REWIND",
		"BriefDescription": "",
		"PublicDescription": ""
		"EventCode": "0x1000A",
		"EventName": "PM_PMC3_REWIND",
		"BriefDescription": "PMC3 rewind event. A rewind happens when a speculative event (such as latency or CPI stack) is selected on PMC3 and the stall reason or reload source did not match the one programmed in PMC3. When this occurs, the count in PMC3 will not change."
		},
		{,
		"EventCode": "0x4003E",
		"EventName": "PM_LD_CMPL",
		"BriefDescription": "count of Loads completed",
		"PublicDescription": ""
		"EventCode": "0x3C058",
		"EventName": "PM_LARX_FIN",
		"BriefDescription": "Larx finished"
		},
		{,
		"EventCode": "0x4C040",
		"EventName": "PM_DATA_FROM_L2_DISP_CONFLICT_OTHER",
		"BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a demand load",
		"PublicDescription": ""
		"EventCode": "0x1C040",
		"EventName": "PM_DATA_FROM_L2_NO_CONFLICT",
		"BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a demand load"
		},
		{,
		"EventCode": "0x4C042",
		"EventName": "PM_DATA_FROM_L3",
		"BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a demand load",
		"PublicDescription": ""
		"EventCode": "0x2C040",
		"EventName": "PM_DATA_FROM_L2_MEPF",
		"BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to a demand load"
		},
		{,
		"EventCode": "0x4C048",
		"EventName": "PM_DATA_FROM_DL2L3_MOD",
		"BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load",
		"PublicDescription": ""
		"EventCode": "0x2E05A",
		"EventName": "PM_LRQ_REJECT",
		"BriefDescription": "Internal LSU reject from LRQ. Rejects cause the load to go back to LRQ, but it stays contained within the LSU once it gets issued. This event counts the number of times the LRQ attempts to relaunch an instruction after a reject. Any load can suffer multiple rejects"
		},
		{,
		"EventCode": "0x2C05C",
		"EventName": "PM_INST_GRP_PUMP_CPRED",
		"BriefDescription": "Initial and Final Pump Scope was group pump (prediction=correct) for an instruction fetch (demand only)"
		},
		{,
		"EventCode": "0x4D056",
		"EventName": "PM_NON_FMA_FLOP_CMPL",
		"BriefDescription": "Non FMA instruction completed",
		"PublicDescription": ""
		"BriefDescription": "Non FMA instruction completed"
		},
		{,
		"EventCode": "0x3E050",
		"EventName": "PM_DARQ1_4_6_ENTRIES",
		"BriefDescription": "Cycles in which 4, 5, or 6 DARQ1 entries (out of 12) are in use"
		}
		]
		No newline at end of file

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