Commit 3c220bf4 authored by Michal Simek's avatar Michal Simek
Browse files

arm: zynq: Label whole PL part as fpga_full region 



This will simplify dt overlay structure for the whole PL.

Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent e5e6f687

arch/arm/boot/dts/zynq-7000.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -42,6 +42,14 @@ 
		};

	};



	fpga_full: fpga-full {

		compatible = "fpga-region";

		fpga-mgr = <&devcfg>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

	};



	pmu@f8891000 {

		compatible = "arm,cortex-a9-pmu";

		interrupts = <0 5 4>, <0 6 4>;

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