dt-bindings: geni-se: Convert QUP geni-se bindings to YAML

Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller

Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper

is a programmable module for supporting a wide range of serial interfaces

like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial

Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP

Wrapper controller is modeled as a node with zero or more child nodes each

representing a serial engine.

Required properties:

- compatible:		Must be "qcom,geni-se-qup".

- reg:			Must contain QUP register address and length.

- clock-names:		Must contain "m-ahb" and "s-ahb".

- clocks:		AHB clocks needed by the device.

Required properties if child node exists:

- #address-cells: 	Must be <1> for Serial Engine Address

- #size-cells: 		Must be <1> for Serial Engine Address Size

- ranges: 		Must be present

Properties for children:

A GENI based QUP wrapper controller node can contain 0 or more child nodes

representing serial devices.  These serial devices can be a QCOM UART, I2C

controller, SPI controller, or some combination of aforementioned devices.

Please refer below the child node definitions for the supported serial

interface protocols.

Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller

Required properties:

- compatible:		Must be "qcom,geni-i2c".

- reg: 			Must contain QUP register address and length.

- interrupts: 		Must contain I2C interrupt.

- clock-names: 		Must contain "se".

- clocks: 		Serial engine core clock needed by the device.

- #address-cells:	Must be <1> for I2C device address.

- #size-cells:		Must be <0> as I2C addresses have no size component.

Optional property:

- clock-frequency:	Desired I2C bus clock frequency in Hz.

			When missing default to 100000Hz.

Child nodes should conform to I2C bus binding as described in i2c.txt.

Qualcomm Technologies Inc. GENI Serial Engine based UART Controller

Required properties:

- compatible:		Must be "qcom,geni-debug-uart" or "qcom,geni-uart".

- reg: 			Must contain UART register location and length.

- interrupts: 		Must contain UART core interrupts.

- clock-names:		Must contain "se".

- clocks:		Serial engine core clock needed by the device.

Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller

node binding is described in

Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt.

Example:

	geniqup@8c0000 {

		compatible = "qcom,geni-se-qup";

		reg = <0x8c0000 0x6000>;

		clock-names = "m-ahb", "s-ahb";

		clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		#address-cells = <1>;

		#size-cells = <1>;

		ranges;

		i2c0: i2c@a94000 {

			compatible = "qcom,geni-i2c";

			reg = <0xa94000 0x4000>;

			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "se";

			clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&qup_1_i2c_5_active>;

			pinctrl-1 = <&qup_1_i2c_5_sleep>;

			#address-cells = <1>;

			#size-cells = <0>;

		};

		uart0: serial@a88000 {

			compatible = "qcom,geni-debug-uart";

			reg = <0xa88000 0x7000>;

			interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;

			clock-names = "se";

			clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;

			pinctrl-names = "default", "sleep";

			pinctrl-0 = <&qup_1_uart_3_active>;

			pinctrl-1 = <&qup_1_uart_3_sleep>;

		};

	}

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: GENI Serial Engine QUP Wrapper Controller

maintainers:

 - Mukesh Savaliya <msavaliy@codeaurora.org>

 - Akash Asthana <akashast@codeaurora.org>

description: |

 Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper

 is a programmable module for supporting a wide range of serial interfaces

 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial

 Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP

 Wrapper controller is modeled as a node with zero or more child nodes each

 representing a serial engine.

properties:

  compatible:

    enum:

      - qcom,geni-se-qup

  reg:

    description: QUP wrapper common register address and length.

    maxItems: 1

  clock-names:

    items:

      - const: m-ahb

      - const: s-ahb

  clocks:

    items:

      - description: Master AHB Clock

      - description: Slave AHB Clock

  "#address-cells":

     const: 2

  "#size-cells":

     const: 2

  ranges: true

required:

  - compatible

  - reg

  - clock-names

  - clocks

  - "#address-cells"

  - "#size-cells"

  - ranges

patternProperties:

  "^.*@[0-9a-f]+$":

    type: object

    description: Common properties for GENI Serial Engine based I2C, SPI and

                 UART controller.

    properties:

      reg:

        description: GENI Serial Engine register address and length.

        maxItems: 1

      clock-names:

        const: se

      clocks:

        description: Serial engine core clock needed by the device.

        maxItems: 1

    required:

      - reg

      - clock-names

      - clocks

  "spi@[0-9a-f]+$":

    type: object

    description: GENI serial engine based SPI controller. SPI in master mode

                 supports up to 50MHz, up to four chip selects, programmable

                 data path from 4 bits to 32 bits and numerous protocol

                 variants.

    allOf:

      - $ref: /spi/spi-controller.yaml#

    properties:

      compatible:

        enum:

          - qcom,geni-spi

      interrupts:

        maxItems: 1

      "#address-cells":

         const: 1

      "#size-cells":

         const: 0

    required:

      - compatible

      - interrupts

      - "#address-cells"

      - "#size-cells"

  "i2c@[0-9a-f]+$":

    type: object

    description: GENI serial engine based I2C controller.

    allOf:

      - $ref: /schemas/i2c/i2c-controller.yaml#

    properties:

      compatible:

        enum:

          - qcom,geni-i2c

      interrupts:

        maxItems: 1

      "#address-cells":

         const: 1

      "#size-cells":

         const: 0

      clock-frequency:

        description: Desired I2C bus clock frequency in Hz.

        default: 100000

    required:

      - compatible

      - interrupts

      - "#address-cells"

      - "#size-cells"

  "serial@[0-9a-f]+$":

    type: object

    description: GENI Serial Engine based UART Controller.

    allOf:

      - $ref: /schemas/serial.yaml#

    properties:

      compatible:

        enum:

          - qcom,geni-uart

          - qcom,geni-debug-uart

      interrupts:

        minItems: 1

        maxItems: 2

        items:

          - description: UART core irq

          - description: Wakeup irq (RX GPIO)

    required:

      - compatible

      - interrupts

examples:

  - |

    #include <dt-bindings/clock/qcom,gcc-sdm845.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {

        #address-cells = <2>;

        #size-cells = <2>;

        geniqup@8c0000 {

            compatible = "qcom,geni-se-qup";

            reg = <0 0x008c0000 0 0x6000>;

            clock-names = "m-ahb", "s-ahb";

            clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

                <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

            #address-cells = <2>;

            #size-cells = <2>;

            ranges;

            i2c0: i2c@a94000 {

                compatible = "qcom,geni-i2c";

                reg = <0 0xa94000 0 0x4000>;

                interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;

                clock-names = "se";

                clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;

                pinctrl-names = "default", "sleep";

                pinctrl-0 = <&qup_1_i2c_5_active>;

                pinctrl-1 = <&qup_1_i2c_5_sleep>;

                #address-cells = <1>;

                #size-cells = <0>;

            };

            uart0: serial@a88000 {

                compatible = "qcom,geni-uart";

                reg = <0 0xa88000 0 0x7000>;

                interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;

                clock-names = "se";

                clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;

                pinctrl-names = "default", "sleep";

                pinctrl-0 = <&qup_1_uart_3_active>;

                pinctrl-1 = <&qup_1_uart_3_sleep>;

            };

        };

    };

...